Operational Voltage Reduction of Flash Memory Using High- \kappa Composite Tunnel Barriers

We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V prog . Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.