Simulation Cost Reduction Strategies for Behavioral Model Verification in Bayesian Based Stopping Rule

This paper presents two additional strategies to reduce simulation time for Bayesian based stopping rules in VHDL model verification. The first is that a semi-random variable is defined and the data staying in the semi-random variable range are skipped when stopping rule is running, and a turning po...

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Bibliographische Detailangaben

Hauptverfasser:	Kim, Kang Chul, Lim, Chang-Gyoon, Yoo, Jae Hung, Han, Seok Bung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences behavioral VHDL model branch coverage Computer science control theory systems Computer systems and distributed systems. User interface Exact sciences and technology semi-random variable Software stopping rule Verification
Online-Zugang:	Volltext
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