A 15-ns 4-Mb CMOS SRAM
A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (T...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1063-1067 |
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| container_end_page | 1067 |
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| container_issue | 5 |
| container_start_page | 1063 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 25 |
| creator | Aizaki, S. Shimizu, T. Ohkawa, M. Abe, K. Aizaki, A. Ando, M. Kudoh, O. Sasaki, I. |
| description | A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55- mu m CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either *4 or *1 can be selected purely electrically, and does not require any pin connection procedure.< > |
| doi_str_mv | 10.1109/4.62125 |
| format | Article |
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An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55- mu m CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either *4 or *1 can be selected purely electrically, and does not require any pin connection procedure.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.62125</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Application software ; Applied sciences ; Circuit testing ; CMOS memory circuits ; CMOS technology ; Decoding ; Driver circuits ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Large-scale systems ; Mirrors ; Random access memory ; Semiconductor electronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Aizaki, S.</creatorcontrib><creatorcontrib>Shimizu, T.</creatorcontrib><creatorcontrib>Ohkawa, M.</creatorcontrib><creatorcontrib>Abe, K.</creatorcontrib><creatorcontrib>Aizaki, A.</creatorcontrib><creatorcontrib>Ando, M.</creatorcontrib><creatorcontrib>Kudoh, O.</creatorcontrib><creatorcontrib>Sasaki, I.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aizaki, S.</au><au>Shimizu, T.</au><au>Ohkawa, M.</au><au>Abe, K.</au><au>Aizaki, A.</au><au>Ando, M.</au><au>Kudoh, O.</au><au>Sasaki, I.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 15-ns 4-Mb CMOS SRAM</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1990-10-01</date><risdate>1990</risdate><volume>25</volume><issue>5</issue><spage>1063</spage><epage>1067</epage><pages>1063-1067</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55- mu m CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either *4 or *1 can be selected purely electrically, and does not require any pin connection procedure.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.62125</doi><tpages>5</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1990-10, Vol.25 (5), p.1063-1067 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_19825618 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application software Applied sciences Circuit testing CMOS memory circuits CMOS technology Decoding Driver circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Large-scale systems Mirrors Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | A 15-ns 4-Mb CMOS SRAM |
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