Reconfigurations in Graphs and Grids
Let G be a connected graph, and let V and V ′ two n-element subsets of its vertex set V(G). Imagine that we place a chip at each element of V and we want to move them into the positions of V ′ (V and V ′ may have common elements). A move is defined as shifting a chip from v1 to v2 (v1,v2 ∈ V(G)) on...
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creator | Calinescu, Gruia Dumitrescu, Adrian Pach, János |
description | Let G be a connected graph, and let V and V ′ two n-element subsets of its vertex set V(G). Imagine that we place a chip at each element of V and we want to move them into the positions of V ′ (V and V ′ may have common elements). A move is defined as shifting a chip from v1 to v2 (v1,v2 ∈ V(G)) on a path formed by edges of G so that no intermediate vertices are occupied. We give upper and lower bounds on the number of moves that are necessary, and analyze the computational complexity of this problem under various assumptions: labeled versus unlabeled chips, arbitrary graphs versus the case when the graph is the rectangular (infinite) planar grid, etc. We provide hardness and inapproximability results for several variants of the problem. We also give a linear-time algorithm which performs an optimal (minimum) number of moves for the unlabeled version in a tree, and a constant-ratio approximation algorithm for the unlabeled version in a graph. The graph algorithm uses the tree algorithm as a subroutine. |
doi_str_mv | 10.1007/11682462_27 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>pascalfrancis_sprin</sourceid><recordid>TN_cdi_pascalfrancis_primary_19689081</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>19689081</sourcerecordid><originalsourceid>FETCH-LOGICAL-p219t-b8f268074d8f7a0223cfab727c563d7b15291c1f84462fa516fcfeec53fab2ee3</originalsourceid><addsrcrecordid>eNpVkEtLAzEUheMLHOqs_ANd6MLFaO7NeymlVqEgiK5DJpPUaJ0ZJnXhvzdSF3o358L5OHAOIedAr4FSdQMgNXKJFtUBqY3STHDKUAkJh6QCCdAwxs3RP0_wY1JRRrExirNTUuf8Rssx0BJ1RS6egh_6mDafk9uloc_z1M9Xkxtf89z1XXlTl8_ISXTbHOpfnZGXu-Xz4r5ZP64eFrfrZkQwu6bVEaWminc6KkcRmY-uVai8kKxTLQg04CFqXlpEJ0BGH0PwghUMQ2AzcrnPHV32bhsn1_uU7TilDzd9WTBSG6qhcFd7Lher34TJtsPwni1Q-7OU_bMU-wbku1PZ</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Reconfigurations in Graphs and Grids</title><source>Springer Books</source><creator>Calinescu, Gruia ; Dumitrescu, Adrian ; Pach, János</creator><contributor>Kiwi, Marcos ; Correa, José R. ; Hevia, Alejandro</contributor><creatorcontrib>Calinescu, Gruia ; Dumitrescu, Adrian ; Pach, János ; Kiwi, Marcos ; Correa, José R. ; Hevia, Alejandro</creatorcontrib><description>Let G be a connected graph, and let V and V ′ two n-element subsets of its vertex set V(G). Imagine that we place a chip at each element of V and we want to move them into the positions of V ′ (V and V ′ may have common elements). A move is defined as shifting a chip from v1 to v2 (v1,v2 ∈ V(G)) on a path formed by edges of G so that no intermediate vertices are occupied. We give upper and lower bounds on the number of moves that are necessary, and analyze the computational complexity of this problem under various assumptions: labeled versus unlabeled chips, arbitrary graphs versus the case when the graph is the rectangular (infinite) planar grid, etc. We provide hardness and inapproximability results for several variants of the problem. We also give a linear-time algorithm which performs an optimal (minimum) number of moves for the unlabeled version in a tree, and a constant-ratio approximation algorithm for the unlabeled version in a graph. The graph algorithm uses the tree algorithm as a subroutine.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 9783540327554</identifier><identifier>ISBN: 354032755X</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 9783540327561</identifier><identifier>EISBN: 3540327568</identifier><identifier>DOI: 10.1007/11682462_27</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Computer science; control theory; systems ; Exact sciences and technology ; Feasible Solution ; Free Vertex ; Intermediate Vertex ; Local Ratio ; Recursive Call ; Theoretical computing</subject><ispartof>LATIN 2006: Theoretical Informatics, 2006, p.262-273</ispartof><rights>Springer-Verlag Berlin Heidelberg 2006</rights><rights>2007 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/11682462_27$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/11682462_27$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>309,310,779,780,784,789,790,793,4050,4051,27925,38255,41442,42511</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=19689081$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><contributor>Kiwi, Marcos</contributor><contributor>Correa, José R.</contributor><contributor>Hevia, Alejandro</contributor><creatorcontrib>Calinescu, Gruia</creatorcontrib><creatorcontrib>Dumitrescu, Adrian</creatorcontrib><creatorcontrib>Pach, János</creatorcontrib><title>Reconfigurations in Graphs and Grids</title><title>LATIN 2006: Theoretical Informatics</title><description>Let G be a connected graph, and let V and V ′ two n-element subsets of its vertex set V(G). Imagine that we place a chip at each element of V and we want to move them into the positions of V ′ (V and V ′ may have common elements). A move is defined as shifting a chip from v1 to v2 (v1,v2 ∈ V(G)) on a path formed by edges of G so that no intermediate vertices are occupied. We give upper and lower bounds on the number of moves that are necessary, and analyze the computational complexity of this problem under various assumptions: labeled versus unlabeled chips, arbitrary graphs versus the case when the graph is the rectangular (infinite) planar grid, etc. We provide hardness and inapproximability results for several variants of the problem. We also give a linear-time algorithm which performs an optimal (minimum) number of moves for the unlabeled version in a tree, and a constant-ratio approximation algorithm for the unlabeled version in a graph. The graph algorithm uses the tree algorithm as a subroutine.</description><subject>Applied sciences</subject><subject>Computer science; control theory; systems</subject><subject>Exact sciences and technology</subject><subject>Feasible Solution</subject><subject>Free Vertex</subject><subject>Intermediate Vertex</subject><subject>Local Ratio</subject><subject>Recursive Call</subject><subject>Theoretical computing</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>9783540327554</isbn><isbn>354032755X</isbn><isbn>9783540327561</isbn><isbn>3540327568</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpVkEtLAzEUheMLHOqs_ANd6MLFaO7NeymlVqEgiK5DJpPUaJ0ZJnXhvzdSF3o358L5OHAOIedAr4FSdQMgNXKJFtUBqY3STHDKUAkJh6QCCdAwxs3RP0_wY1JRRrExirNTUuf8Rssx0BJ1RS6egh_6mDafk9uloc_z1M9Xkxtf89z1XXlTl8_ISXTbHOpfnZGXu-Xz4r5ZP64eFrfrZkQwu6bVEaWminc6KkcRmY-uVai8kKxTLQg04CFqXlpEJ0BGH0PwghUMQ2AzcrnPHV32bhsn1_uU7TilDzd9WTBSG6qhcFd7Lher34TJtsPwni1Q-7OU_bMU-wbku1PZ</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Calinescu, Gruia</creator><creator>Dumitrescu, Adrian</creator><creator>Pach, János</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2006</creationdate><title>Reconfigurations in Graphs and Grids</title><author>Calinescu, Gruia ; Dumitrescu, Adrian ; Pach, János</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p219t-b8f268074d8f7a0223cfab727c563d7b15291c1f84462fa516fcfeec53fab2ee3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Applied sciences</topic><topic>Computer science; control theory; systems</topic><topic>Exact sciences and technology</topic><topic>Feasible Solution</topic><topic>Free Vertex</topic><topic>Intermediate Vertex</topic><topic>Local Ratio</topic><topic>Recursive Call</topic><topic>Theoretical computing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Calinescu, Gruia</creatorcontrib><creatorcontrib>Dumitrescu, Adrian</creatorcontrib><creatorcontrib>Pach, János</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Calinescu, Gruia</au><au>Dumitrescu, Adrian</au><au>Pach, János</au><au>Kiwi, Marcos</au><au>Correa, José R.</au><au>Hevia, Alejandro</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Reconfigurations in Graphs and Grids</atitle><btitle>LATIN 2006: Theoretical Informatics</btitle><date>2006</date><risdate>2006</risdate><spage>262</spage><epage>273</epage><pages>262-273</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>9783540327554</isbn><isbn>354032755X</isbn><eisbn>9783540327561</eisbn><eisbn>3540327568</eisbn><abstract>Let G be a connected graph, and let V and V ′ two n-element subsets of its vertex set V(G). Imagine that we place a chip at each element of V and we want to move them into the positions of V ′ (V and V ′ may have common elements). A move is defined as shifting a chip from v1 to v2 (v1,v2 ∈ V(G)) on a path formed by edges of G so that no intermediate vertices are occupied. We give upper and lower bounds on the number of moves that are necessary, and analyze the computational complexity of this problem under various assumptions: labeled versus unlabeled chips, arbitrary graphs versus the case when the graph is the rectangular (infinite) planar grid, etc. We provide hardness and inapproximability results for several variants of the problem. We also give a linear-time algorithm which performs an optimal (minimum) number of moves for the unlabeled version in a tree, and a constant-ratio approximation algorithm for the unlabeled version in a graph. The graph algorithm uses the tree algorithm as a subroutine.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11682462_27</doi><tpages>12</tpages></addata></record> |
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identifier | ISSN: 0302-9743 |
ispartof | LATIN 2006: Theoretical Informatics, 2006, p.262-273 |
issn | 0302-9743 1611-3349 |
language | eng |
recordid | cdi_pascalfrancis_primary_19689081 |
source | Springer Books |
subjects | Applied sciences Computer science control theory systems Exact sciences and technology Feasible Solution Free Vertex Intermediate Vertex Local Ratio Recursive Call Theoretical computing |
title | Reconfigurations in Graphs and Grids |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T10%3A39%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_sprin&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Reconfigurations%20in%20Graphs%20and%20Grids&rft.btitle=LATIN%202006:%20Theoretical%20Informatics&rft.au=Calinescu,%20Gruia&rft.date=2006&rft.spage=262&rft.epage=273&rft.pages=262-273&rft.issn=0302-9743&rft.eissn=1611-3349&rft.isbn=9783540327554&rft.isbn_list=354032755X&rft_id=info:doi/10.1007/11682462_27&rft_dat=%3Cpascalfrancis_sprin%3E19689081%3C/pascalfrancis_sprin%3E%3Curl%3E%3C/url%3E&rft.eisbn=9783540327561&rft.eisbn_list=3540327568&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |