Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2006-12, Vol.14 (12), p.1379-1383 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Chen Kong Teh Hamada, M. Fujita, T. Hara, H. Ikumi, N. Oowaki, Y. |
| description | This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size |
| doi_str_mv | 10.1109/TVLSI.2006.887833 |
| format | Article |
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We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2006.887833</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Amplifiers ; Applied sciences ; Circuit properties ; Clocks ; CMOS digital integrated circuits ; Consumption ; Delay ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Digital integrated circuits ; Dynamical systems ; Dynamics ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Flip-flops ; High speed integrated circuits ; Integrated circuits ; Latches ; low-power integrated circuits ; Mapping ; MOS devices ; Power dissipation ; Research and development ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; System-on-a-chip ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1379-1383</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c354t-bdc9910c5c73737d0be01da3338bf02ec385c93cabb34cf9efcd1dc3359259753</citedby><cites>FETCH-LOGICAL-c354t-bdc9910c5c73737d0be01da3338bf02ec385c93cabb34cf9efcd1dc3359259753</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4052355$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4052355$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18458385$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Chen Kong Teh</creatorcontrib><creatorcontrib>Hamada, M.</creatorcontrib><creatorcontrib>Fujita, T.</creatorcontrib><creatorcontrib>Hara, H.</creatorcontrib><creatorcontrib>Ikumi, N.</creatorcontrib><creatorcontrib>Oowaki, Y.</creatorcontrib><title>Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size</description><subject>Amplifiers</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Clocks</subject><subject>CMOS digital integrated circuits</subject><subject>Consumption</subject><subject>Delay</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Digital integrated circuits</subject><subject>Dynamical systems</subject><subject>Dynamics</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Flip-flops</subject><subject>High speed integrated circuits</subject><subject>Integrated circuits</subject><subject>Latches</subject><subject>low-power integrated circuits</subject><subject>Mapping</subject><subject>MOS devices</subject><subject>Power dissipation</subject><subject>Research and development</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>System-on-a-chip</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkFFLwzAQgIsoOKc_QHwpgvjUeWmaNXmU6dyg6mDT15Cm6Yy0TU06xv69mR0K3j3cwX13cF8QXCIYIQTsbvWeLeejGGA8ojSlGB8FA0RIGjEfx76HMY5ojOA0OHPuEwAlCYNB8DIxTaE7bRpRhQ-iE-GzaFvdrMNppdtoWpnWhaWxYWa20cJslQ1FU4Qzvf6IFsr6SS0aqcLlznWqdufBSSkqpy4OdRi8TR9Xk1mUvT7NJ_dZJDFJuigvJGMIJJEp9llArgAVAmNM8xJiJTElkmEp8hwnsmSqlAUqJMaExYSlBA-D2_5ua83XRrmO19pJVVWiUWbjOKUsQYDGiSev_5GfZmP9t44zFHsLkO4h1EPSGuesKnlrdS3sjiPge7_8xy_f--W9X79zczgsnBRVab0H7f4WaUKof8NzVz2nlVK_4wRIjAnB3y38gww</recordid><startdate>20061201</startdate><enddate>20061201</enddate><creator>Chen Kong Teh</creator><creator>Hamada, M.</creator><creator>Fujita, T.</creator><creator>Hara, H.</creator><creator>Ikumi, N.</creator><creator>Oowaki, Y.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Testing</topic><topic>Digital circuits</topic><topic>Digital integrated circuits</topic><topic>Dynamical systems</topic><topic>Dynamics</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Flip-flops</topic><topic>High speed integrated circuits</topic><topic>Integrated circuits</topic><topic>Latches</topic><topic>low-power integrated circuits</topic><topic>Mapping</topic><topic>MOS devices</topic><topic>Power dissipation</topic><topic>Research and development</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>System-on-a-chip</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chen Kong Teh</creatorcontrib><creatorcontrib>Hamada, M.</creatorcontrib><creatorcontrib>Fujita, T.</creatorcontrib><creatorcontrib>Hara, H.</creatorcontrib><creatorcontrib>Ikumi, N.</creatorcontrib><creatorcontrib>Oowaki, Y.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen Kong Teh</au><au>Hamada, M.</au><au>Fujita, T.</au><au>Hara, H.</au><au>Ikumi, N.</au><au>Oowaki, Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2006-12-01</date><risdate>2006</risdate><volume>14</volume><issue>12</issue><spage>1379</spage><epage>1383</epage><pages>1379-1383</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2006.887833</doi><tpages>5</tpages></addata></record> |
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| subjects | Amplifiers Applied sciences Circuit properties Clocks CMOS digital integrated circuits Consumption Delay Design. Technologies. Operation analysis. Testing Digital circuits Digital integrated circuits Dynamical systems Dynamics Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Flip-flops High speed integrated circuits Integrated circuits Latches low-power integrated circuits Mapping MOS devices Power dissipation Research and development Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices System-on-a-chip Very large scale integration |
| title | Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems |
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