A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature I/sub on/= 820...

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Hauptverfasser: Boeuf, F., Arnaud, F., Basso, M.T., Sotta, D., Wacquant, F., Rosa, J., Bicais-Lepinay, N., Bernard, H., Bustos, J., Manakli, S., Gaillardin, M., Grant, J., Skotnicki, T., Tavel, B., Duriez, B., Bidaud, M., Gouraud, P., Chaton, C., Morin, P., Todeschini, J., Jurdit, M., Pain, L., De-Jonghe, V., El-Farhane, R., Jullian, S.
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Sprache:eng
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Zusammenfassung:In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature I/sub on/= 820/spl mu/A//spl mu/m/340 /spl mu/A//spl mu/m at I/sub off/ = 20nA//spl mu/m at V/sub dd/=1.0V. RO features Tp < 10ps. LP devices feature I/sub on/= 505 /spl mu/A//spl mu/m 1240 /spl mu/A//spl mu/m at I/sub off/ = 0.1 nA//spl mu/m at V/sub dd/= 1.2V. In addition, high-voltage 50A/2.5V devices are made to complete the CMOS platform.
DOI:10.1109/IEDM.2004.1419177