Sizing consideration for leakage control transistor

In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy...

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Bibliographische Detailangaben
Hauptverfasser:	Farbiz, F., Farazian, M., Emadi, M., Sadeghi, K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Automatic control Circuit simulation Delay Electric, optical and optoelectronic circuits Electronics Exact sciences and technology Iterative algorithms Leakage current Neural networks Other multijunction devices. Power transistors. Thyristors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SPICE Threshold voltage Transistors Very large scale integration
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Beschreibung
Zusammenfassung:	In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.
DOI:	10.1109/ICVD.2004.1260992