Characterization of split gate flash memory endurance degradation mechanism
In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to domi...
Gespeichert in:
| Hauptverfasser: | , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 117 |
|---|---|
| container_issue | |
| container_start_page | 115 |
| container_title | |
| container_volume | |
| creator | Wu, T.I. Chih, Y.D. Chen, S.H. Wang, W. Mi-Chang Chang Shih, J.R. Chin, H.W. Wu, K. |
| description | In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to dominate the weak erase failure. However from this study, it is found that cell current reduction after erase is not due to erase-induced tunneling oxide degradation. On the contrary, program-induced electron trapping in the coupling oxide dominates the cell current reduction after long term endurance cycling stress. |
| doi_str_mv | 10.1109/IPFA.2004.1345561 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>pascalfrancis_6IE</sourceid><recordid>TN_cdi_pascalfrancis_primary_17624279</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1345561</ieee_id><sourcerecordid>17624279</sourcerecordid><originalsourceid>FETCH-LOGICAL-i135t-161015355b7cd803fb22d6aaa22852b500572ef2e607a826f5978b53e0d9ebaf3</originalsourceid><addsrcrecordid>eNpFUMtKxEAQHBBBWfMB4mUuHhPnkc7juARXFxf0oOelk-nZjOTFTDysX28kgk1DH6q6qCrGbqVIpBTlw_5tt02UEGkidQqQyQsWlXkhltVFCilcsSiET7GMLqEo5DV7qVr02Mzk3TfObhz4aHmYOjfzE87EbYeh5T31oz9zGsyXx6Ehbujk0awPPTUtDi70N-zSYhco-rsb9rF7fK-e48Pr077aHmInNcyxzKSQoAHqvDGLM1srZTJEVKoAVYMQkCuyijKRY6EyC0uGGjQJU1KNVm_Y_ao7YWiws7-WXDhO3vXoz0eZZypVebnw7laeI6J_eK1G_wCbFlk-</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Characterization of split gate flash memory endurance degradation mechanism</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Wu, T.I. ; Chih, Y.D. ; Chen, S.H. ; Wang, W. ; Mi-Chang Chang ; Shih, J.R. ; Chin, H.W. ; Wu, K.</creator><creatorcontrib>Wu, T.I. ; Chih, Y.D. ; Chen, S.H. ; Wang, W. ; Mi-Chang Chang ; Shih, J.R. ; Chin, H.W. ; Wu, K.</creatorcontrib><description>In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to dominate the weak erase failure. However from this study, it is found that cell current reduction after erase is not due to erase-induced tunneling oxide degradation. On the contrary, program-induced electron trapping in the coupling oxide dominates the cell current reduction after long term endurance cycling stress.</description><identifier>ISBN: 9780780384545</identifier><identifier>ISBN: 0780384547</identifier><identifier>DOI: 10.1109/IPFA.2004.1345561</identifier><language>eng</language><publisher>Piscataway NJ: IEEE</publisher><subject>Applied sciences ; Character generation ; Degradation ; Design. Technologies. Operation analysis. Testing ; Electron traps ; Electronics ; Exact sciences and technology ; Failure analysis ; Flash memory ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Nonvolatile memory ; Performance evaluation ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Split gate flash memory cells ; Testing ; Tunneling</subject><ispartof>Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743), 2004, p.115-117</ispartof><rights>2006 INIST-CNRS</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1345561$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1345561$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17624279$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Wu, T.I.</creatorcontrib><creatorcontrib>Chih, Y.D.</creatorcontrib><creatorcontrib>Chen, S.H.</creatorcontrib><creatorcontrib>Wang, W.</creatorcontrib><creatorcontrib>Mi-Chang Chang</creatorcontrib><creatorcontrib>Shih, J.R.</creatorcontrib><creatorcontrib>Chin, H.W.</creatorcontrib><creatorcontrib>Wu, K.</creatorcontrib><title>Characterization of split gate flash memory endurance degradation mechanism</title><title>Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743)</title><addtitle>IPFA</addtitle><description>In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to dominate the weak erase failure. However from this study, it is found that cell current reduction after erase is not due to erase-induced tunneling oxide degradation. On the contrary, program-induced electron trapping in the coupling oxide dominates the cell current reduction after long term endurance cycling stress.</description><subject>Applied sciences</subject><subject>Character generation</subject><subject>Degradation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electron traps</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Failure analysis</subject><subject>Flash memory</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Nonvolatile memory</subject><subject>Performance evaluation</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Split gate flash memory cells</subject><subject>Testing</subject><subject>Tunneling</subject><isbn>9780780384545</isbn><isbn>0780384547</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUMtKxEAQHBBBWfMB4mUuHhPnkc7juARXFxf0oOelk-nZjOTFTDysX28kgk1DH6q6qCrGbqVIpBTlw_5tt02UEGkidQqQyQsWlXkhltVFCilcsSiET7GMLqEo5DV7qVr02Mzk3TfObhz4aHmYOjfzE87EbYeh5T31oz9zGsyXx6Ehbujk0awPPTUtDi70N-zSYhco-rsb9rF7fK-e48Pr077aHmInNcyxzKSQoAHqvDGLM1srZTJEVKoAVYMQkCuyijKRY6EyC0uGGjQJU1KNVm_Y_ao7YWiws7-WXDhO3vXoz0eZZypVebnw7laeI6J_eK1G_wCbFlk-</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Wu, T.I.</creator><creator>Chih, Y.D.</creator><creator>Chen, S.H.</creator><creator>Wang, W.</creator><creator>Mi-Chang Chang</creator><creator>Shih, J.R.</creator><creator>Chin, H.W.</creator><creator>Wu, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>Characterization of split gate flash memory endurance degradation mechanism</title><author>Wu, T.I. ; Chih, Y.D. ; Chen, S.H. ; Wang, W. ; Mi-Chang Chang ; Shih, J.R. ; Chin, H.W. ; Wu, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i135t-161015355b7cd803fb22d6aaa22852b500572ef2e607a826f5978b53e0d9ebaf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Character generation</topic><topic>Degradation</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electron traps</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Failure analysis</topic><topic>Flash memory</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Nonvolatile memory</topic><topic>Performance evaluation</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Split gate flash memory cells</topic><topic>Testing</topic><topic>Tunneling</topic><toplevel>online_resources</toplevel><creatorcontrib>Wu, T.I.</creatorcontrib><creatorcontrib>Chih, Y.D.</creatorcontrib><creatorcontrib>Chen, S.H.</creatorcontrib><creatorcontrib>Wang, W.</creatorcontrib><creatorcontrib>Mi-Chang Chang</creatorcontrib><creatorcontrib>Shih, J.R.</creatorcontrib><creatorcontrib>Chin, H.W.</creatorcontrib><creatorcontrib>Wu, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wu, T.I.</au><au>Chih, Y.D.</au><au>Chen, S.H.</au><au>Wang, W.</au><au>Mi-Chang Chang</au><au>Shih, J.R.</au><au>Chin, H.W.</au><au>Wu, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Characterization of split gate flash memory endurance degradation mechanism</atitle><btitle>Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743)</btitle><stitle>IPFA</stitle><date>2004</date><risdate>2004</risdate><spage>115</spage><epage>117</epage><pages>115-117</pages><isbn>9780780384545</isbn><isbn>0780384547</isbn><abstract>In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to dominate the weak erase failure. However from this study, it is found that cell current reduction after erase is not due to erase-induced tunneling oxide degradation. On the contrary, program-induced electron trapping in the coupling oxide dominates the cell current reduction after long term endurance cycling stress.</abstract><cop>Piscataway NJ</cop><pub>IEEE</pub><doi>10.1109/IPFA.2004.1345561</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9780780384545 |
| ispartof | Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743), 2004, p.115-117 |
| issn | |
| language | eng |
| recordid | cdi_pascalfrancis_primary_17624279 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Character generation Degradation Design. Technologies. Operation analysis. Testing Electron traps Electronics Exact sciences and technology Failure analysis Flash memory Integrated circuits Integrated circuits by function (including memories and processors) Nonvolatile memory Performance evaluation Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Split gate flash memory cells Testing Tunneling |
| title | Characterization of split gate flash memory endurance degradation mechanism |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T15%3A50%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Characterization%20of%20split%20gate%20flash%20memory%20endurance%20degradation%20mechanism&rft.btitle=Proceedings%20of%20the%2011th%20International%20Symposium%20on%20the%20Physical%20and%20Failure%20Analysis%20of%20Integrated%20Circuits.%20IPFA%202004%20(IEEE%20Cat.%20No.04TH8743)&rft.au=Wu,%20T.I.&rft.date=2004&rft.spage=115&rft.epage=117&rft.pages=115-117&rft.isbn=9780780384545&rft.isbn_list=0780384547&rft_id=info:doi/10.1109/IPFA.2004.1345561&rft_dat=%3Cpascalfrancis_6IE%3E17624279%3C/pascalfrancis_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1345561&rfr_iscdi=true |