A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically s...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2006-01, Vol.41 (1), p.146-151 |
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| container_end_page | 151 |
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| container_issue | 1 |
| container_start_page | 146 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 41 |
| creator | Kevin Zhang Bhattacharya, U. Zhanping Chen Hamzaoglu, F. Murray, D. Vallepalli, N. Yih Wang Bo Zheng Bohr, M. |
| description | Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption. |
| doi_str_mv | 10.1109/JSSC.2005.859025 |
| format | Article |
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The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2005.859025</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Arrays ; CMOS ; CMOS technology ; Design optimization ; Design. Technologies. Operation analysis. Testing ; Dynamic power supply ; Dynamics ; Electric potential ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Energy consumption ; Exact sciences and technology ; Frequency synchronization ; Integrated circuit noise ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; MOS memory integrated circuits ; Power consumption ; Power supplies ; Random access memory ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon ; SRAM cell ; Stability ; static noise margin (SNM) ; Static random access memory ; static random-access memory (SRAM) ; Threshold voltage ; Voltage ; write margin</subject><ispartof>IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.146-151</ispartof><rights>2006 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.</description><subject>Applied sciences</subject><subject>Arrays</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Design optimization</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dynamic power supply</subject><subject>Dynamics</subject><subject>Electric potential</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Frequency synchronization</subject><subject>Integrated circuit noise</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>MOS memory integrated circuits</subject><subject>Power consumption</subject><subject>Power supplies</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>SRAM cell</subject><subject>Stability</subject><subject>static noise margin (SNM)</subject><subject>Static random access memory</subject><subject>static random-access memory (SRAM)</subject><subject>Threshold voltage</subject><subject>Voltage</subject><subject>write margin</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kUtLAzEURoMoWB97wU0Q1FVqMnlNlqX4RBGsghsJmUymHZmXyQxSf70pLRRcuAqX79ybmxwATggeE4LV1cNsNh0nGPNxyhVO-A4YEc5TRCR93wUjjEmKVMz3wUEIn7FkLCUj8DGBFN3e_UCJUZ3B2cvkCZYNFBw1NZw-Pc9g7-yiaat2voTfZb-Iae_m3vQuh7athrpBmQmxyJeNqUsLu_bbeRiGrquWR2CvMFVwx5vzELzdXL9O79Dj8-39dPKILE1pjwRxzDBBisxgxnAmRU4yrESupHRCCadYIU1mZJ7JxClKhRVFlhBZGJLghNFDcLme2_n2a3Ch13UZrKsq07h2CDpVgijJcRrJi3_JRCqZMEYiePYH_GwH38RXaBUvVav_ixBeQ9a3IXhX6M6XtfFLTbBeadErLXqlRa-1xJbzzVwTrKkKbxpbhm2fjFriCpE7XXOlc24bc8Eo5_QXVb6SiA</recordid><startdate>200601</startdate><enddate>200601</enddate><creator>Kevin Zhang</creator><creator>Bhattacharya, U.</creator><creator>Zhanping Chen</creator><creator>Hamzaoglu, F.</creator><creator>Murray, D.</creator><creator>Vallepalli, N.</creator><creator>Yih Wang</creator><creator>Bo Zheng</creator><creator>Bohr, M.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| ispartof | IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.146-151 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Arrays CMOS CMOS technology Design optimization Design. Technologies. Operation analysis. Testing Dynamic power supply Dynamics Electric potential Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Energy consumption Exact sciences and technology Frequency synchronization Integrated circuit noise Integrated circuits Integrated circuits by function (including memories and processors) MOS memory integrated circuits Power consumption Power supplies Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon SRAM cell Stability static noise margin (SNM) Static random access memory static random-access memory (SRAM) Threshold voltage Voltage write margin |
| title | A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply |
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