Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data &...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2006-01, Vol.41 (1), p.135-145
Hauptverfasser:	Ohsawa, T., Fujita, K., Hatsuda, K., Higashi, T., Shino, T., Minami, Y., Nakajima, H., Morikado, M., Inoh, K., Hamamoto, T., Watanabe, S., Fujii, S., Furuyama, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	1T-DRAM Amplifiers Applied sciences Asymmetry Capacitance capacitorless DRAM Capacitors Charge Charge pumps Circuit properties Circuits Computer simulation Contacts Degradation Design. Technologies. Operation analysis. Testing Dummies Dynamic random access memory Electric, optical and optoelectronic circuits Electronic circuits Electronics embedded memory Exact sciences and technology floating body cell Immune system Integrated circuits Integrated circuits by function (including memories and processors) Material storage Monte Carlo methods Monte Carlo simulation Pumping Random access memory Research and development Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices silicon-on-insulator technology System-on-a-chip
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