Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper pr...
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| creator | Aragón, Juan L. Veidenbaum, Alexander V. |
| description | Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8- and 16-wide issue processor in 100nm technology. Results show an average improvement in the I-cache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance. |
| doi_str_mv | 10.1007/11572961_3 |
| format | Conference Proceeding |
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Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8- and 16-wide issue processor in 100nm technology. Results show an average improvement in the I-cache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 3540296433</identifier><identifier>ISBN: 9783540296430</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 9783540321088</identifier><identifier>EISBN: 354032108X</identifier><identifier>DOI: 10.1007/11572961_3</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Branch Prediction ; Branch Predictor ; Cache Line ; Computers, microcomputers ; Electronics ; Exact sciences and technology ; Hardware ; Instruction Cache ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8- and 16-wide issue processor in 100nm technology. Results show an average improvement in the I-cache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.</description><subject>Applied sciences</subject><subject>Branch Prediction</subject><subject>Branch Predictor</subject><subject>Cache Line</subject><subject>Computers, microcomputers</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Instruction Cache</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Translation Lookaside Buffer</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>3540296433</isbn><isbn>9783540296430</isbn><isbn>9783540321088</isbn><isbn>354032108X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpFkE1LAzEUReMX2NZu_AWzEdyMvuRlJsmylKkWCrqwuAxJJqmjdaYkU6H_3ikVXN0L53AXl5BbCg8UQDxSWgimSqrxjEyVkFhwQEZBynMyoiWlOSJXF2R8BIPIES_JCBBYrgTHazJO6RMAmFBsRGZV6-PmkFcheNc3Pz5btqmP-6F3bbbwvfvI1m3TZ6GL2XtTDzylvc9eY-d8Sl1MN-QqmG3y07-ckPWieps_56uXp-V8tsp3jMo-R4PKuRIVFzWaoKwBrMFwyZSXvgZbI9hgbSgL5JZbUMjQcWcKJSmogBNyd9rdmeTMNkTTuibpXWy-TTxoKnihOBSDd3_y0oDajY_adt1X0hT08T_9_x_-ApJpXLY</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Aragón, Juan L.</creator><creator>Veidenbaum, Alexander V.</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2005</creationdate><title>Energy-Effective Instruction Fetch Unit for Wide Issue Processors</title><author>Aragón, Juan L. ; Veidenbaum, Alexander V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p218t-3a39cc63947d3af9ba03d0a4829e8ed0bd30bfbbf6534b4b09323c4ca598109f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Applied sciences</topic><topic>Branch Prediction</topic><topic>Branch Predictor</topic><topic>Cache Line</topic><topic>Computers, microcomputers</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Instruction Cache</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Semiconductor electronics. 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Solid state devices</topic><topic>Translation Lookaside Buffer</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Aragón, Juan L.</creatorcontrib><creatorcontrib>Veidenbaum, Alexander V.</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Aragón, Juan L.</au><au>Veidenbaum, Alexander V.</au><au>Xue, Jingling</au><au>Srikanthan, Thambipillai</au><au>Chang, Chip-Hong</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Energy-Effective Instruction Fetch Unit for Wide Issue Processors</atitle><btitle>Advances in Computer Systems Architecture</btitle><date>2005</date><risdate>2005</risdate><spage>15</spage><epage>27</epage><pages>15-27</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>3540296433</isbn><isbn>9783540296430</isbn><eisbn>9783540321088</eisbn><eisbn>354032108X</eisbn><abstract>Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8- and 16-wide issue processor in 100nm technology. Results show an average improvement in the I-cache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11572961_3</doi><tpages>13</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Advances in Computer Systems Architecture, 2005, p.15-27 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_17459405 |
| source | Springer Books |
| subjects | Applied sciences Branch Prediction Branch Predictor Cache Line Computers, microcomputers Electronics Exact sciences and technology Hardware Instruction Cache Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Translation Lookaside Buffer |
| title | Energy-Effective Instruction Fetch Unit for Wide Issue Processors |
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