Simple design formula for parallel plate mode suppression by ground via-holes
In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppressio...
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| creator | Yuasa, T. Nishino, T. Oh-Hashi, H. |
| description | In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposing formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance. |
| doi_str_mv | 10.1109/MWSYM.2004.1336067 |
| format | Conference Proceeding |
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Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposing formula. 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No.04CH37535)</title><addtitle>MWSYM</addtitle><description>In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposing formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.</description><subject>Applied sciences</subject><subject>Circuit optimization</subject><subject>Computational modeling</subject><subject>Coupling circuits</subject><subject>Degradation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dielectric substrates</subject><subject>Electronics</subject><subject>Equivalent circuits</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Millimeter wave circuits</subject><subject>Millimeter wave technology</subject><subject>Packaging</subject><subject>Radio frequency</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0149-645X</issn><issn>2576-7216</issn><isbn>0780383311</isbn><isbn>9780780383319</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkE1LAzEYhIMfYK39A3rJxePW90022exRil_Q4qGKeirv7iY1kt0NGyv039tSwbnMYR4GZhi7RJgiQnmzeFt-LKYCIJ-ilBp0ccRGQhU6KwTqY3YOhQFppEQ8YSPAvMx0rt7P2CSlL9gpVzmiGrHF0rcxWN7Y5Ncdd_3QbgLtnUcaKAQbeAz0bXnbN5anTYyDTcn3Ha-2fD30m67hP56yzz7YdMFOHYVkJ38-Zq_3dy-zx2z-_PA0u51nHtF8Z9oJU4gSjXW5qQwZqoVS2jpoStINUaUECBROAUhHQKXWu21NXe2CuizlmF0feiOlmoIbqKt9WsXBtzRsV1jkqpCw564OnLfW_seHx-QvFARdsQ</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Yuasa, T.</creator><creator>Nishino, T.</creator><creator>Oh-Hashi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2004</creationdate><title>Simple design formula for parallel plate mode suppression by ground via-holes</title><author>Yuasa, T. ; Nishino, T. ; Oh-Hashi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i118t-6f2872918ef48b8a8ac2556ef0d9a6daab520212f5003fa0a966576dcbb52c993</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Circuit optimization</topic><topic>Computational modeling</topic><topic>Coupling circuits</topic><topic>Degradation</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Dielectric substrates</topic><topic>Electronics</topic><topic>Equivalent circuits</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Millimeter wave circuits</topic><topic>Millimeter wave technology</topic><topic>Packaging</topic><topic>Radio frequency</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>online_resources</toplevel><creatorcontrib>Yuasa, T.</creatorcontrib><creatorcontrib>Nishino, T.</creatorcontrib><creatorcontrib>Oh-Hashi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yuasa, T.</au><au>Nishino, T.</au><au>Oh-Hashi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Simple design formula for parallel plate mode suppression by ground via-holes</atitle><btitle>2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)</btitle><stitle>MWSYM</stitle><date>2004</date><risdate>2004</risdate><volume>2</volume><spage>641</spage><epage>644 Vol.2</epage><pages>641-644 Vol.2</pages><issn>0149-645X</issn><eissn>2576-7216</eissn><isbn>0780383311</isbn><isbn>9780780383319</isbn><abstract>In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposing formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.</abstract><cop>Piscataway NJ</cop><pub>IEEE</pub><doi>10.1109/MWSYM.2004.1336067</doi></addata></record> |
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| issn | 0149-645X 2576-7216 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Circuit optimization Computational modeling Coupling circuits Degradation Design. Technologies. Operation analysis. Testing Dielectric substrates Electronics Equivalent circuits Exact sciences and technology Integrated circuits Millimeter wave circuits Millimeter wave technology Packaging Radio frequency Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Simple design formula for parallel plate mode suppression by ground via-holes |
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