Hardware Support for Multithreaded Execution of Loops with Limited Parallelism
Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extension...
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| creator | Dimitriou, Georgios Polychronopoulos, Constantine |
| description | Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism. |
| doi_str_mv | 10.1007/11573036_59 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>pascalfrancis_sprin</sourceid><recordid>TN_cdi_pascalfrancis_primary_17437565</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>17437565</sourcerecordid><originalsourceid>FETCH-LOGICAL-p219t-f4b9acde184a36b8cb76fa81d5b8657e5c012a43a897b31b5c024c92ec4c4ef83</originalsourceid><addsrcrecordid>eNpNkMtOwzAURM1Loi1d8QPesGAR8PUjjpeoKhQpPCRgHd04DgTSOrITFf6eVGXBajQ6o5FmCDkHdgWM6WsApQUTaaHMAZkKJZngzAAckgmkAIkQ0hyRudHZjnGTaqGPyYQJxhOjpTgl0xg_GWNcGz4hjysM1RaDoy9D1_nQ09oH-jC0fdN_BIeVq-jy29mhb_yG-prm3neRbkdK82bd9CN_xoBt69omrs_ISY1tdPM_nZG32-XrYpXkT3f3i5s86TiYPqlladBWDjKJIi0zW-q0xgwqVWap0k5ZBhylwMzoUkA5ei6t4c5KK12diRm52Pd2GC22dcCNbWLRhWaN4aeAcahWqRpzl_tcHNHm3YWi9P4rFsCK3ZvFvzfFL2QaYp4</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Hardware Support for Multithreaded Execution of Loops with Limited Parallelism</title><source>Springer Books</source><creator>Dimitriou, Georgios ; Polychronopoulos, Constantine</creator><contributor>Bozanis, Panayiotis ; Houstis, Elias N.</contributor><creatorcontrib>Dimitriou, Georgios ; Polychronopoulos, Constantine ; Bozanis, Panayiotis ; Houstis, Elias N.</creatorcontrib><description>Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 9783540296737</identifier><identifier>ISBN: 3540296735</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 3540320911</identifier><identifier>EISBN: 9783540320913</identifier><identifier>DOI: 10.1007/11573036_59</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Computer science; control theory; systems ; Context Switch ; Exact sciences and technology ; Hardware Support ; Loop Schedule ; Reorder Buffer ; Synthetic Benchmark</subject><ispartof>Advances in Informatics, 2005, p.622-632</ispartof><rights>Springer-Verlag Berlin Heidelberg 2005</rights><rights>2006 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/11573036_59$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/11573036_59$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>309,310,779,780,784,789,790,793,4050,4051,27925,38255,41442,42511</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17437565$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><contributor>Bozanis, Panayiotis</contributor><contributor>Houstis, Elias N.</contributor><creatorcontrib>Dimitriou, Georgios</creatorcontrib><creatorcontrib>Polychronopoulos, Constantine</creatorcontrib><title>Hardware Support for Multithreaded Execution of Loops with Limited Parallelism</title><title>Advances in Informatics</title><description>Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism.</description><subject>Applied sciences</subject><subject>Computer science; control theory; systems</subject><subject>Context Switch</subject><subject>Exact sciences and technology</subject><subject>Hardware Support</subject><subject>Loop Schedule</subject><subject>Reorder Buffer</subject><subject>Synthetic Benchmark</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>9783540296737</isbn><isbn>3540296735</isbn><isbn>3540320911</isbn><isbn>9783540320913</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpNkMtOwzAURM1Loi1d8QPesGAR8PUjjpeoKhQpPCRgHd04DgTSOrITFf6eVGXBajQ6o5FmCDkHdgWM6WsApQUTaaHMAZkKJZngzAAckgmkAIkQ0hyRudHZjnGTaqGPyYQJxhOjpTgl0xg_GWNcGz4hjysM1RaDoy9D1_nQ09oH-jC0fdN_BIeVq-jy29mhb_yG-prm3neRbkdK82bd9CN_xoBt69omrs_ISY1tdPM_nZG32-XrYpXkT3f3i5s86TiYPqlladBWDjKJIi0zW-q0xgwqVWap0k5ZBhylwMzoUkA5ei6t4c5KK12diRm52Pd2GC22dcCNbWLRhWaN4aeAcahWqRpzl_tcHNHm3YWi9P4rFsCK3ZvFvzfFL2QaYp4</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Dimitriou, Georgios</creator><creator>Polychronopoulos, Constantine</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2005</creationdate><title>Hardware Support for Multithreaded Execution of Loops with Limited Parallelism</title><author>Dimitriou, Georgios ; Polychronopoulos, Constantine</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p219t-f4b9acde184a36b8cb76fa81d5b8657e5c012a43a897b31b5c024c92ec4c4ef83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Applied sciences</topic><topic>Computer science; control theory; systems</topic><topic>Context Switch</topic><topic>Exact sciences and technology</topic><topic>Hardware Support</topic><topic>Loop Schedule</topic><topic>Reorder Buffer</topic><topic>Synthetic Benchmark</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Dimitriou, Georgios</creatorcontrib><creatorcontrib>Polychronopoulos, Constantine</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Dimitriou, Georgios</au><au>Polychronopoulos, Constantine</au><au>Bozanis, Panayiotis</au><au>Houstis, Elias N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Hardware Support for Multithreaded Execution of Loops with Limited Parallelism</atitle><btitle>Advances in Informatics</btitle><date>2005</date><risdate>2005</risdate><spage>622</spage><epage>632</epage><pages>622-632</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>9783540296737</isbn><isbn>3540296735</isbn><eisbn>3540320911</eisbn><eisbn>9783540320913</eisbn><abstract>Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11573036_59</doi><tpages>11</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Advances in Informatics, 2005, p.622-632 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_17437565 |
| source | Springer Books |
| subjects | Applied sciences Computer science control theory systems Context Switch Exact sciences and technology Hardware Support Loop Schedule Reorder Buffer Synthetic Benchmark |
| title | Hardware Support for Multithreaded Execution of Loops with Limited Parallelism |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T19%3A48%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_sprin&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Hardware%20Support%20for%20Multithreaded%20Execution%20of%20Loops%20with%20Limited%20Parallelism&rft.btitle=Advances%20in%20Informatics&rft.au=Dimitriou,%20Georgios&rft.date=2005&rft.spage=622&rft.epage=632&rft.pages=622-632&rft.issn=0302-9743&rft.eissn=1611-3349&rft.isbn=9783540296737&rft.isbn_list=3540296735&rft_id=info:doi/10.1007/11573036_59&rft_dat=%3Cpascalfrancis_sprin%3E17437565%3C/pascalfrancis_sprin%3E%3Curl%3E%3C/url%3E&rft.eisbn=3540320911&rft.eisbn_list=9783540320913&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |