Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly...
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| creator | Geiger, Michael J. McKee, Sally A. Tyson, Gary S. |
| description | Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application. |
| doi_str_mv | 10.1007/11587514_8 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>pascalfrancis_sprin</sourceid><recordid>TN_cdi_pascalfrancis_primary_17415808</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>17415808</sourcerecordid><originalsourceid>FETCH-LOGICAL-p218t-d7705d2a2b0825a1582ea7775a38d59c2e73cf8119c77b9932f9566754cca48a3</originalsourceid><addsrcrecordid>eNpFkMtOwzAQRc1LopRu-AJvkNgE_Ihjmx2NCkWqBKKwjiaOk1q0SWSnSOXrMS0Sq7kz9-poZhC6ouSWEiLvKBVKCpoW6ghdcJESzphk6hiNaEZpwnmqT9BES7X3CKcyO0WjqFiiZcrP0SQEVxJCtVaM8hFqpnbXtRWeQnAGv9nGdS3Owaxc29zjZW-Ng7X7jt1-avFy8FszbL0NuO48nrtmhV-tj3oDrbEYImzWWt_scN61wfovGCLzEp3VsA528lfH6ONx9p7Pk8XL03P-sEh6RtWQVFISUTFgJVFMQLyWWZBSCuCqEtowK7mpFaXaSFlqzVmtRZZJkRoDqQI-RtcHbg_BwLr2cSkXit67DfhdQWUamUTF3M0hF6LVNtYXZdd9hoKS4vfRxf-j-Q8C5WpP</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation</title><source>Springer Books</source><creator>Geiger, Michael J. ; McKee, Sally A. ; Tyson, Gary S.</creator><contributor>Navarro, Nacho ; Ungerer, Theo ; Valero, Mateo ; Hwu, Wen-mei W. ; Conte, Tom</contributor><creatorcontrib>Geiger, Michael J. ; McKee, Sally A. ; Tyson, Gary S. ; Navarro, Nacho ; Ungerer, Theo ; Valero, Mateo ; Hwu, Wen-mei W. ; Conte, Tom</creatorcontrib><description>Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 9783540303176</identifier><identifier>ISBN: 3540303170</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 3540322728</identifier><identifier>EISBN: 9783540322726</identifier><identifier>DOI: 10.1007/11587514_8</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Cache Line ; Cache Size ; Computer science; control theory; systems ; Data Cache ; Dynamic Voltage Scaling ; Exact sciences and technology ; Memory and file management (including protection and security) ; Memory organisation. Data processing ; Memory Reference ; Software</subject><ispartof>High Performance Embedded Architectures and Compilers, 2005, p.102-115</ispartof><rights>Springer-Verlag Berlin Heidelberg 2005</rights><rights>2006 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/11587514_8$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/11587514_8$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>309,310,779,780,784,789,790,793,4048,4049,27924,38254,41441,42510</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17415808$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><contributor>Navarro, Nacho</contributor><contributor>Ungerer, Theo</contributor><contributor>Valero, Mateo</contributor><contributor>Hwu, Wen-mei W.</contributor><contributor>Conte, Tom</contributor><creatorcontrib>Geiger, Michael J.</creatorcontrib><creatorcontrib>McKee, Sally A.</creatorcontrib><creatorcontrib>Tyson, Gary S.</creatorcontrib><title>Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation</title><title>High Performance Embedded Architectures and Compilers</title><description>Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application.</description><subject>Applied sciences</subject><subject>Cache Line</subject><subject>Cache Size</subject><subject>Computer science; control theory; systems</subject><subject>Data Cache</subject><subject>Dynamic Voltage Scaling</subject><subject>Exact sciences and technology</subject><subject>Memory and file management (including protection and security)</subject><subject>Memory organisation. Data processing</subject><subject>Memory Reference</subject><subject>Software</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>9783540303176</isbn><isbn>3540303170</isbn><isbn>3540322728</isbn><isbn>9783540322726</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpFkMtOwzAQRc1LopRu-AJvkNgE_Ihjmx2NCkWqBKKwjiaOk1q0SWSnSOXrMS0Sq7kz9-poZhC6ouSWEiLvKBVKCpoW6ghdcJESzphk6hiNaEZpwnmqT9BES7X3CKcyO0WjqFiiZcrP0SQEVxJCtVaM8hFqpnbXtRWeQnAGv9nGdS3Owaxc29zjZW-Ng7X7jt1-avFy8FszbL0NuO48nrtmhV-tj3oDrbEYImzWWt_scN61wfovGCLzEp3VsA528lfH6ONx9p7Pk8XL03P-sEh6RtWQVFISUTFgJVFMQLyWWZBSCuCqEtowK7mpFaXaSFlqzVmtRZZJkRoDqQI-RtcHbg_BwLr2cSkXit67DfhdQWUamUTF3M0hF6LVNtYXZdd9hoKS4vfRxf-j-Q8C5WpP</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Geiger, Michael J.</creator><creator>McKee, Sally A.</creator><creator>Tyson, Gary S.</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2005</creationdate><title>Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation</title><author>Geiger, Michael J. ; McKee, Sally A. ; Tyson, Gary S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p218t-d7705d2a2b0825a1582ea7775a38d59c2e73cf8119c77b9932f9566754cca48a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Applied sciences</topic><topic>Cache Line</topic><topic>Cache Size</topic><topic>Computer science; control theory; systems</topic><topic>Data Cache</topic><topic>Dynamic Voltage Scaling</topic><topic>Exact sciences and technology</topic><topic>Memory and file management (including protection and security)</topic><topic>Memory organisation. Data processing</topic><topic>Memory Reference</topic><topic>Software</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Geiger, Michael J.</creatorcontrib><creatorcontrib>McKee, Sally A.</creatorcontrib><creatorcontrib>Tyson, Gary S.</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Geiger, Michael J.</au><au>McKee, Sally A.</au><au>Tyson, Gary S.</au><au>Navarro, Nacho</au><au>Ungerer, Theo</au><au>Valero, Mateo</au><au>Hwu, Wen-mei W.</au><au>Conte, Tom</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation</atitle><btitle>High Performance Embedded Architectures and Compilers</btitle><date>2005</date><risdate>2005</risdate><spage>102</spage><epage>115</epage><pages>102-115</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>9783540303176</isbn><isbn>3540303170</isbn><eisbn>3540322728</eisbn><eisbn>9783540322726</eisbn><abstract>Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11587514_8</doi><tpages>14</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | High Performance Embedded Architectures and Compilers, 2005, p.102-115 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_17415808 |
| source | Springer Books |
| subjects | Applied sciences Cache Line Cache Size Computer science control theory systems Data Cache Dynamic Voltage Scaling Exact sciences and technology Memory and file management (including protection and security) Memory organisation. Data processing Memory Reference Software |
| title | Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T10%3A36%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_sprin&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Beyond%20Basic%20Region%20Caching:%20Specializing%20Cache%20Structures%20for%20High%20Performance%20and%20Energy%20Conservation&rft.btitle=High%20Performance%20Embedded%20Architectures%20and%20Compilers&rft.au=Geiger,%20Michael%20J.&rft.date=2005&rft.spage=102&rft.epage=115&rft.pages=102-115&rft.issn=0302-9743&rft.eissn=1611-3349&rft.isbn=9783540303176&rft.isbn_list=3540303170&rft_id=info:doi/10.1007/11587514_8&rft_dat=%3Cpascalfrancis_sprin%3E17415808%3C/pascalfrancis_sprin%3E%3Curl%3E%3C/url%3E&rft.eisbn=3540322728&rft.eisbn_list=9783540322726&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |