On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures

The performance improvement of a number of motion estimation algorithms are evaluated following vector/SIMD instruction set extensions for MPEG-2 TM5 video encoding. Simulation-based results indicate a substantial complexity metric reduction for Full-Search, Three Step Search, Four Step Search and Diamond Search making the later three appropriate for execution on a high performance embedded VLSI platform. A simple model is developed to explain the simulated results, and a compound performance/power metric, the complexity-power-product (CPP), is proposed for algorithmic optimisation in vectorized applications for low-power, consumer devices.