FPGA-Efficient Hybrid LUT/CORDIC Architecture

The paper presents a hybrid architecture for digital polar-to-Cartesian (i.e. phase-to-I/Q) designs. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources. FPGA resource utilization, timing and power consumption as well as accuracy of calculated...

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Hauptverfasser:	Janiszewski, Ireneusz, Meuth, Hermann, Hoppe, Berhard
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Computer science control theory systems CORDIC Algorithm CORDIC Iteration Electronics Exact sciences and technology FPGA Resource Hybrid Architecture Integrated circuits Integrated circuits by function (including memories and processors) Language processing and microprogramming Numerically Control Oscillator Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Software
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creator	Janiszewski, Ireneusz Meuth, Hermann Hoppe, Berhard
description	The paper presents a hybrid architecture for digital polar-to-Cartesian (i.e. phase-to-I/Q) designs. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources. FPGA resource utilization, timing and power consumption as well as accuracy of calculated results may be optimised consistently in comparison to conventional pure CORDIC algorithm implementations.
doi_str_mv	10.1007/978-3-540-30117-2_102
format	Conference Proceeding
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source	Springer Books
subjects	Applied sciences Computer science control theory systems CORDIC Algorithm CORDIC Iteration Electronics Exact sciences and technology FPGA Resource Hybrid Architecture Integrated circuits Integrated circuits by function (including memories and processors) Language processing and microprogramming Numerically Control Oscillator Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Software
title	FPGA-Efficient Hybrid LUT/CORDIC Architecture
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