Characterization and parameterized generation of synthetic combinational benchmark circuits
The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for gene...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1998-10, Vol.17 (10), p.985-996 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 17 |
| creator | Hutton, M.D. Rose, J. Grossman, J.P. Corneil, D.G. |
| description | The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs. |
| doi_str_mv | 10.1109/43.728919 |
| format | Article |
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Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hutton, M.D.</creatorcontrib><creatorcontrib>Rose, J.</creatorcontrib><creatorcontrib>Grossman, J.P.</creatorcontrib><creatorcontrib>Corneil, D.G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hutton, M.D.</au><au>Rose, J.</au><au>Grossman, J.P.</au><au>Corneil, D.G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Characterization and parameterized generation of synthetic combinational benchmark circuits</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1998-10-01</date><risdate>1998</risdate><volume>17</volume><issue>10</issue><spage>985</spage><epage>996</epage><pages>985-996</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1998-10, Vol.17 (10), p.985-996 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_1609122 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Automatic testing Benchmark testing Character generation Circuit testing Delay Design automation Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Field programmable gate arrays Integrated circuits Logic arrays Packaging Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Characterization and parameterized generation of synthetic combinational benchmark circuits |
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