Enhancement mode PHEMT low noise amplifier with LNA linearity control (IP3) and mitigated bypass switch
A new LNA has been designed using single supply enhancement mode PHEMT process for WCDMA and other wireless application up to 6 GHz. The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0...
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| creator | Kumar, S. Vice, M. Morkner, H. Wayne, L. |
| description | A new LNA has been designed using single supply enhancement mode PHEMT process for WCDMA and other wireless application up to 6 GHz. The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0 V) switch has been design for bypass-mitigated switch. In high linearity mode the LNA draws 8.5 mA current and has 15 dB gain, 1 dB noise figure, -6 dBm IP/sub 1dB,/, 7.3 dBm IIP3 with I/O return loss >11 dB. In low linearity mode the LNA draws 3.5 mA current and has 14 dB gain, 1.1 dB noise figure,, -6.5 dBm IP/sub 1dB,/, 2 dBm IIP3 with I/O return loss >11 dB. The LNA bypass-mitigated switch has 11 dB and draws negligible current with 3/0 V logic, /spl sim/200 /spl mu/A for 0/3 V logic. Due to well-behaved match of LNA in High Linearity/Low Linearity/Bypass modes, this LNA has minimum mismatch effect for duplexers; and filters in a receiver system. |
| doi_str_mv | 10.1109/RFIC.2002.1012034 |
| format | Conference Proceeding |
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The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0 V) switch has been design for bypass-mitigated switch. In high linearity mode the LNA draws 8.5 mA current and has 15 dB gain, 1 dB noise figure, -6 dBm IP/sub 1dB,/, 7.3 dBm IIP3 with I/O return loss >11 dB. In low linearity mode the LNA draws 3.5 mA current and has 14 dB gain, 1.1 dB noise figure,, -6.5 dBm IP/sub 1dB,/, 2 dBm IIP3 with I/O return loss >11 dB. The LNA bypass-mitigated switch has <3.5 dB insertion loss and NF, I/O return loss >11 dB and draws negligible current with 3/0 V logic, /spl sim/200 /spl mu/A for 0/3 V logic. Due to well-behaved match of LNA in High Linearity/Low Linearity/Bypass modes, this LNA has minimum mismatch effect for duplexers; and filters in a receiver system.</description><identifier>ISSN: 1529-2517</identifier><identifier>ISBN: 0780372468</identifier><identifier>ISBN: 9780780372467</identifier><identifier>EISSN: 2375-0995</identifier><identifier>DOI: 10.1109/RFIC.2002.1012034</identifier><language>eng</language><publisher>Piscataway NJ: IEEE</publisher><subject>Amplifiers ; Applied sciences ; Circuit properties ; CMOS logic circuits ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Gain ; Insertion loss ; Linearity ; Logic design ; Low-noise amplifiers ; Multiaccess communication ; Noise figure ; PHEMTs ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Switches ; Switching, multiplexing, switched capacity circuits ; Transistors</subject><ispartof>2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. 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Digest of Papers (Cat. No.02CH37280)</title><addtitle>RFIC</addtitle><description>A new LNA has been designed using single supply enhancement mode PHEMT process for WCDMA and other wireless application up to 6 GHz. The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0 V) switch has been design for bypass-mitigated switch. In high linearity mode the LNA draws 8.5 mA current and has 15 dB gain, 1 dB noise figure, -6 dBm IP/sub 1dB,/, 7.3 dBm IIP3 with I/O return loss >11 dB. In low linearity mode the LNA draws 3.5 mA current and has 14 dB gain, 1.1 dB noise figure,, -6.5 dBm IP/sub 1dB,/, 2 dBm IIP3 with I/O return loss >11 dB. The LNA bypass-mitigated switch has <3.5 dB insertion loss and NF, I/O return loss >11 dB and draws negligible current with 3/0 V logic, /spl sim/200 /spl mu/A for 0/3 V logic. Due to well-behaved match of LNA in High Linearity/Low Linearity/Bypass modes, this LNA has minimum mismatch effect for duplexers; and filters in a receiver system.</description><subject>Amplifiers</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>CMOS logic circuits</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gain</subject><subject>Insertion loss</subject><subject>Linearity</subject><subject>Logic design</subject><subject>Low-noise amplifiers</subject><subject>Multiaccess communication</subject><subject>Noise figure</subject><subject>PHEMTs</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Switches</subject><subject>Switching, multiplexing, switched capacity circuits</subject><subject>Transistors</subject><issn>1529-2517</issn><issn>2375-0995</issn><isbn>0780372468</isbn><isbn>9780780372467</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkEtLQzEQhYMPsNb-AHGTjaCLW_NskqWU1haqFqnrkuRO2sh9lJtA6b_3QgXPZhbnmxnOQeiekjGlxLx8zZfTMSOEjSmhjHBxgQaMK1kQY-QluiVKE66YmOgrNKCSmYJJqm7QKKUf0ktIQagaoN2s2dvGQw1NxnVbAl4vZu8bXLVH3LQxAbb1oYohQoePMe_x6uMVV7EB28V8wr5tctdW-Gm55s_YNiWuY447m6HE7nSwKeHUr_n9HboOtkow-ptD9D2fbaaLYvX5tpy-ropIucyFI0IzG4KyYF1QzAQ70VASb6QTCkBQyxV46Q1VznldBjMpeR_WKeK8oHyIHs93-9_eVqHrw8W0PXSxtt1pS6XWXAjTcw9nLgLAv33ukv8C1-pmJw</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Kumar, S.</creator><creator>Vice, M.</creator><creator>Morkner, H.</creator><creator>Wayne, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2002</creationdate><title>Enhancement mode PHEMT low noise amplifier with LNA linearity control (IP3) and mitigated bypass switch</title><author>Kumar, S. ; Vice, M. ; Morkner, H. ; Wayne, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i135t-b0482aff7aeabf729fa68ed0c95b47ee41a37ec5c917bbc8df96d3078b70bc413</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Amplifiers</topic><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>CMOS logic circuits</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gain</topic><topic>Insertion loss</topic><topic>Linearity</topic><topic>Logic design</topic><topic>Low-noise amplifiers</topic><topic>Multiaccess communication</topic><topic>Noise figure</topic><topic>PHEMTs</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Switches</topic><topic>Switching, multiplexing, switched capacity circuits</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Kumar, S.</creatorcontrib><creatorcontrib>Vice, M.</creatorcontrib><creatorcontrib>Morkner, H.</creatorcontrib><creatorcontrib>Wayne, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kumar, S.</au><au>Vice, M.</au><au>Morkner, H.</au><au>Wayne, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Enhancement mode PHEMT low noise amplifier with LNA linearity control (IP3) and mitigated bypass switch</atitle><btitle>2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280)</btitle><stitle>RFIC</stitle><date>2002</date><risdate>2002</risdate><spage>213</spage><epage>216</epage><pages>213-216</pages><issn>1529-2517</issn><eissn>2375-0995</eissn><isbn>0780372468</isbn><isbn>9780780372467</isbn><abstract>A new LNA has been designed using single supply enhancement mode PHEMT process for WCDMA and other wireless application up to 6 GHz. The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0 V) switch has been design for bypass-mitigated switch. In high linearity mode the LNA draws 8.5 mA current and has 15 dB gain, 1 dB noise figure, -6 dBm IP/sub 1dB,/, 7.3 dBm IIP3 with I/O return loss >11 dB. In low linearity mode the LNA draws 3.5 mA current and has 14 dB gain, 1.1 dB noise figure,, -6.5 dBm IP/sub 1dB,/, 2 dBm IIP3 with I/O return loss >11 dB. The LNA bypass-mitigated switch has <3.5 dB insertion loss and NF, I/O return loss >11 dB and draws negligible current with 3/0 V logic, /spl sim/200 /spl mu/A for 0/3 V logic. Due to well-behaved match of LNA in High Linearity/Low Linearity/Bypass modes, this LNA has minimum mismatch effect for duplexers; and filters in a receiver system.</abstract><cop>Piscataway NJ</cop><pub>IEEE</pub><doi>10.1109/RFIC.2002.1012034</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 1529-2517 |
| ispartof | 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280), 2002, p.213-216 |
| issn | 1529-2517 2375-0995 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Amplifiers Applied sciences Circuit properties CMOS logic circuits Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Gain Insertion loss Linearity Logic design Low-noise amplifiers Multiaccess communication Noise figure PHEMTs Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switches Switching, multiplexing, switched capacity circuits Transistors |
| title | Enhancement mode PHEMT low noise amplifier with LNA linearity control (IP3) and mitigated bypass switch |
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