A design approach to passive interconnects for single flux quantum logic circuits
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to prev...
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| Veröffentlicht in: | IEEE transactions on applied superconductivity 2003-06, Vol.13 (2), p.535-538 |
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| container_end_page | 538 |
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| container_issue | 2 |
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| container_title | IEEE transactions on applied superconductivity |
| container_volume | 13 |
| creator | Hashimoto, Y. Yorozu, S. Kameda, Y. Semenov, V.K. |
| description | We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%. |
| doi_str_mv | 10.1109/TASC.2003.813929 |
| format | Article |
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In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.</description><identifier>ISSN: 1051-8223</identifier><identifier>EISSN: 1558-2515</identifier><identifier>DOI: 10.1109/TASC.2003.813929</identifier><identifier>CODEN: ITASE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit properties ; Circuit testing ; Delay effects ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Distributed parameter circuits ; Electric, optical and optoelectronic circuits ; Electrical engineering. Electrical power engineering ; Electromagnets ; Electronic circuits ; Electronics ; Exact sciences and technology ; Impedance ; Integrated circuit interconnections ; Integrated circuits ; Josephson junctions ; Laboratories ; Logic circuits ; Power transmission lines ; Semiconductor electronics. Microelectronics. Optoelectronics. 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In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuit testing</subject><subject>Delay effects</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Distributed parameter circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electrical engineering. Electrical power engineering</subject><subject>Electromagnets</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Impedance</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>Josephson junctions</subject><subject>Laboratories</subject><subject>Logic circuits</subject><subject>Power transmission lines</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Superconducting transmission lines</subject><subject>Testing, measurement, noise and reliability</subject><subject>Various equipment and components</subject><issn>1051-8223</issn><issn>1558-2515</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEUhYMoWKt7wU1AdDc1j7kzmWUpvqAgYl2HNI-aMs20yYzov3fqCAVX58L9zuFwELqkZEIpqe4W07fZhBHCJ4LyilVHaEQBRMaAwnF_E6CZYIyforOU1oTQXOQwQq9TbGzyq4DVdhsbpT9w2-CtSsl_WuxDa6NuQrC6Tdg1EScfVrXFru6-8K5Toe02uG5WXmPto-58m87RiVN1shd_OkbvD_eL2VM2f3l8nk3nmeZA2qwsq6VxYCxwbZaKMaJKU0JFXMFMYUqucqVzzXLmKsFsBZXLuYJeqOKGL_kY3Q65fe1dZ1MrNz5pW9cq2KZLkglWUiHyHrz-B66bLoa-m6SEikKQkkNPkYHSsUkpWie30W9U_O4huV9Y7heW-4XlsHBvufkLVkmr2kUVtE8HHwDw_Je7GjhvrT28GaUFCP4DIMKEUg</recordid><startdate>20030601</startdate><enddate>20030601</enddate><creator>Hashimoto, Y.</creator><creator>Yorozu, S.</creator><creator>Kameda, Y.</creator><creator>Semenov, V.K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Testing</topic><topic>Digital circuits</topic><topic>Distributed parameter circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electrical engineering. Electrical power engineering</topic><topic>Electromagnets</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Impedance</topic><topic>Integrated circuit interconnections</topic><topic>Integrated circuits</topic><topic>Josephson junctions</topic><topic>Laboratories</topic><topic>Logic circuits</topic><topic>Power transmission lines</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Superconducting transmission lines</topic><topic>Testing, measurement, noise and reliability</topic><topic>Various equipment and components</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hashimoto, Y.</creatorcontrib><creatorcontrib>Yorozu, S.</creatorcontrib><creatorcontrib>Kameda, Y.</creatorcontrib><creatorcontrib>Semenov, V.K.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on applied superconductivity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hashimoto, Y.</au><au>Yorozu, S.</au><au>Kameda, Y.</au><au>Semenov, V.K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A design approach to passive interconnects for single flux quantum logic circuits</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>2003-06-01</date><risdate>2003</risdate><volume>13</volume><issue>2</issue><spage>535</spage><epage>538</epage><pages>535-538</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TASC.2003.813929</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit properties Circuit testing Delay effects Design. Technologies. Operation analysis. Testing Digital circuits Distributed parameter circuits Electric, optical and optoelectronic circuits Electrical engineering. Electrical power engineering Electromagnets Electronic circuits Electronics Exact sciences and technology Impedance Integrated circuit interconnections Integrated circuits Josephson junctions Laboratories Logic circuits Power transmission lines Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Superconducting transmission lines Testing, measurement, noise and reliability Various equipment and components |
| title | A design approach to passive interconnects for single flux quantum logic circuits |
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