Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S
The design of all-digital symbol timing synchronizers for FPGAs is a complex task. There are several architectures available for VLSI wireless transceivers but porting them to a software defined radio (SDR) platform is not straightforward. In this paper we report a receiver architecture prepared to...
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Format: | Buchkapitel |
Sprache: | eng |
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Zusammenfassung: | The design of all-digital symbol timing synchronizers for FPGAs is a complex task. There are several architectures available for VLSI wireless transceivers but porting them to a software defined radio (SDR) platform is not straightforward. In this paper we report a receiver architecture prepared to support demanding protocols such as satellite digital video broadcast (DVB-S). In addition, we report hardware implementation and area utilization estimation. Finally we present implementation results of a DVB-S digital receiver on a Virtex-II Pro FPGA. |
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ISSN: | 0302-9743 1611-3349 |
DOI: | 10.1007/978-3-540-45234-8_4 |