Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext,...

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Bibliographische Detailangaben

Hauptverfasser:	Rouvroy, Gaël, Standaert, François-Xavier, Quisquater, Jean-Jacques, Legat, Jean-Didier
Format:	Buchkapitel
Sprache:	eng
Schlagworte:	Applied sciences cryptography DES design methodology efficient implementations Electronics Exact sciences and technology FPGA Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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