Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES
In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext,...
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| creator | Rouvroy, Gaël Standaert, François-Xavier Quisquater, Jean-Jacques Legat, Jean-Didier |
| description | In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description. |
| doi_str_mv | 10.1007/978-3-540-45234-8_19 |
| format | Book Chapter |
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In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.</description><subject>Applied sciences</subject><subject>cryptography</subject><subject>DES</subject><subject>design methodology</subject><subject>efficient implementations</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FPGA</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>3540408223</isbn><isbn>9783540408222</isbn><isbn>3540452346</isbn><isbn>9783540452348</isbn><fulltext>true</fulltext><rsrctype>book_chapter</rsrctype><creationdate>2003</creationdate><recordtype>book_chapter</recordtype><recordid>eNotUU1TFTEQjKIWT-QfeMjFYzQfu9nEG_XgIVVQUIDnVJKdfUT3yyQc9MwPN7u8ucxMd08fphH6zOhXRmnzTTeKCFJXlFQ1FxVRhuk36KMoyArIt2jDJGNEiEofHQiqOBfv0IYKyoluKvFhEclKqobqY3Sa0i9aSnDBuNygl3NIYT_ihxxthn2AhO3Y4pupDV2AFhfaxzDnMI0J5wnflnEI_wBvw_wEEe_uLs_w1TD3MMCY7ar7jnc25dVnOw2z9RnfQ3ruc8LdFPH5xcPKPRbfHkhZP6H3ne0TnB76Cfq5u3jc_iDXt5dX27NrMvOGZyKlAwtQK0VbqbXyrpWNb2VbOS5b33WNc5Voeae8dprXvsCOcQfcVpKDFCfoy6vvbJO3fRft6EMycwyDjX8Nq2uqRbPo-KsuFWrcQzRumn4nw6hZgjElGCNM-bZZczBLMOVIHMzj9OcZUjawXPnylmh7_2TnDDEZQZViihleG04b8R-hP41C</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Rouvroy, Gaël</creator><creator>Standaert, François-Xavier</creator><creator>Quisquater, Jean-Jacques</creator><creator>Legat, Jean-Didier</creator><general>Springer Berlin / Heidelberg</general><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>FFUUA</scope><scope>IQODW</scope></search><sort><creationdate>2003</creationdate><title>Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES</title><author>Rouvroy, Gaël ; Standaert, François-Xavier ; Quisquater, Jean-Jacques ; Legat, Jean-Didier</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p272t-66beaee5880d6998cbd67cd6d4b26dcff7bb43d2f8c9b925cb26b12be2a462e63</frbrgroupid><rsrctype>book_chapters</rsrctype><prefilter>book_chapters</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Applied sciences</topic><topic>cryptography</topic><topic>DES</topic><topic>design methodology</topic><topic>efficient implementations</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>FPGA</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Rouvroy, Gaël</creatorcontrib><creatorcontrib>Standaert, François-Xavier</creatorcontrib><creatorcontrib>Quisquater, Jean-Jacques</creatorcontrib><creatorcontrib>Legat, Jean-Didier</creatorcontrib><collection>ProQuest Ebook Central - Book Chapters - Demo use only</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Rouvroy, Gaël</au><au>Standaert, François-Xavier</au><au>Quisquater, Jean-Jacques</au><au>Legat, Jean-Didier</au><au>Sousa, Jose T. de</au><au>Constantinides, Georg A</au><au>Cheung, Peter Y. K</au><au>Constantinides, George A.</au><au>Y. K. Cheung, Peter</au><format>book</format><genre>bookitem</genre><ristype>CHAP</ristype><atitle>Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES</atitle><btitle>Field Programmable Logic and Application</btitle><seriestitle>Lecture Notes in Computer Science</seriestitle><date>2003</date><risdate>2003</risdate><volume>2778</volume><spage>181</spage><epage>193</epage><pages>181-193</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>3540408223</isbn><isbn>9783540408222</isbn><eisbn>3540452346</eisbn><eisbn>9783540452348</eisbn><abstract>In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.</abstract><cop>Germany</cop><pub>Springer Berlin / Heidelberg</pub><doi>10.1007/978-3-540-45234-8_19</doi><oclcid>166468709</oclcid><tpages>13</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Field Programmable Logic and Application, 2003, Vol.2778, p.181-193 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_15509376 |
| source | Springer Books |
| subjects | Applied sciences cryptography DES design methodology efficient implementations Electronics Exact sciences and technology FPGA Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES |
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