Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations

A run-time reconfiguable array of multipliers architecture is introduced. The novel multiplier can be easily reconfigured to trade bitwidth for array size, thus maximizing the utilization of available hardware, multiply signed or unsigned data, and uses part of its structure when needed. The propose...

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Bibliographische Detailangaben

Hauptverfasser:	Koutroumpezis, G., Tatas, K., Soudris, D., Blionas, S., Masselos, K., Thanailakis, A.
Format:	Buchkapitel
Sprache:	eng
Schlagworte:	Applied sciences Architecture Design Electric, optical and optoelectronic circuits Electronics Exact sciences and technology Interface Unit Reconfigurable Architecture Reconfigurable Array Reconfigurable Computing Theoretical study. Circuits analysis and design
Online-Zugang:	Volltext
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