Skewed CMOS: noise-tolerant high-performance low-power static circuit family
In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins....
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2002-08, Vol.10 (4), p.469-476 |
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| container_end_page | 476 |
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| container_issue | 4 |
| container_start_page | 469 |
| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 10 |
| creator | Solomatnikov, A. Somasekhar, D. Sirisantana, N. Roy, K. |
| description | In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load. |
| doi_str_mv | 10.1109/TVLSI.2002.800519 |
| format | Article |
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Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2002.800519</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Circuit noise ; Circuit properties ; Circuits ; Clocks ; CMOS ; CMOS logic circuits ; Delay ; Design methodology ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic ; Logic circuits ; Logic design ; Low voltage ; Multipliers ; Noise ; Power measurement ; Scalability ; Semiconductor electronics. Microelectronics. Optoelectronics. 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(IEEE) 2002</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c383t-8829d244041cbba0c66943f327bfc348603bc059fcac3b1df3b21d79953d54783</citedby><cites>FETCH-LOGICAL-c383t-8829d244041cbba0c66943f327bfc348603bc059fcac3b1df3b21d79953d54783</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1177345$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27911,27912,54745</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1177345$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=14525298$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Solomatnikov, A.</creatorcontrib><creatorcontrib>Somasekhar, D.</creatorcontrib><creatorcontrib>Sirisantana, N.</creatorcontrib><creatorcontrib>Roy, K.</creatorcontrib><title>Skewed CMOS: noise-tolerant high-performance low-power static circuit family</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.</description><subject>Applied sciences</subject><subject>Circuit noise</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS logic circuits</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Low voltage</subject><subject>Multipliers</subject><subject>Noise</subject><subject>Power measurement</subject><subject>Scalability</subject><subject>Semiconductor electronics. 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Solid state devices</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kU1Lw0AQhoMoWD9-gHgJgnpKnf1Kdr1J8aNQ8VD1umw2u7o1zdbdhNJ_b2oLBQ_OZQbmmZeZeZPkDMEQIRA3r--T6XiIAfCQAzAk9pIBYqzIRB_7fQ05yThGcJgcxTgDQJQKGCST6ZdZmiodPb9Mb9PGu2iy1tcmqKZNP93HZ7YwwfowV402ae2X2cIvTUhjq1qnU-2C7lybWjV39eokObCqjuZ0m4-Tt4f719FTNnl5HI_uJpkmnLQZ51hUmFKgSJelAp3nghJLcFFaTSjPgZQamLBaaVKiypISo6oQgpGK0YKT4-R6o7sI_rszsZVzF7Wpa9UY30UpoIcLjHFPXv1LYp4jlPO15MUfcOa70PRXSIEJoEIw0UNoA-ngYwzGykVwcxVWEoFc2yB_bZBrG-TGhn7mciusola17R-rXdwNUoYZFusFzjecM8bs2qgoCGXkB1kKj1w</recordid><startdate>20020801</startdate><enddate>20020801</enddate><creator>Solomatnikov, A.</creator><creator>Somasekhar, D.</creator><creator>Sirisantana, N.</creator><creator>Roy, K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Solid state devices</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Solomatnikov, A.</creatorcontrib><creatorcontrib>Somasekhar, D.</creatorcontrib><creatorcontrib>Sirisantana, N.</creatorcontrib><creatorcontrib>Roy, K.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Solomatnikov, A.</au><au>Somasekhar, D.</au><au>Sirisantana, N.</au><au>Roy, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Skewed CMOS: noise-tolerant high-performance low-power static circuit family</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2002-08-01</date><risdate>2002</risdate><volume>10</volume><issue>4</issue><spage>469</spage><epage>476</epage><pages>469-476</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2002.800519</doi><tpages>8</tpages></addata></record> |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.469-476 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit noise Circuit properties Circuits Clocks CMOS CMOS logic circuits Delay Design methodology Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic Logic circuits Logic design Low voltage Multipliers Noise Power measurement Scalability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Very large scale integration |
| title | Skewed CMOS: noise-tolerant high-performance low-power static circuit family |
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