Self-Testing of Linear Segments in User-Programmed FPGAs
A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buchkapitel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 174 |
|---|---|
| container_issue | |
| container_start_page | 169 |
| container_title | |
| container_volume | 1896 |
| creator | Tomaszewicz, Pawel |
| description | A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single-or multi-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented. |
| doi_str_mv | 10.1007/3-540-44614-1_19 |
| format | Book Chapter |
| fullrecord | <record><control><sourceid>proquest_pasca</sourceid><recordid>TN_cdi_pascalfrancis_primary_1382992</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EBC3073213_24_185</sourcerecordid><originalsourceid>FETCH-LOGICAL-p1829-3348619f269c21305c7b33741ca0b45654d0fa0362d520eedb8d7357529dfb943</originalsourceid><addsrcrecordid>eNotUDtPwzAQNk8RSnfGDKwuPp8dx2OFaEGqRKW2s-UkTgi0SbHLwL_HaXvLSfc97u4j5BHYBBhTz0ilYFSIDAQFA_qC3GOcHAdwSRLIACii0FdkrFU-YJnKtYZrkjBknGol8JYkWuaSA5f6joxD-GKxkCNwnZB85bY1XbtwaLsm7et00XbO-nTlmp3rDiFtu3QTnKdL3zfe7nauSmfL-TQ8kJvaboMbn_uIbGav65c3uviYv79MF3QPOdfDdXkGuuaZLjkgk6UqEJWA0rJCyEyKitWWYcYryZlzVZFXCqWSXFd1oQWOyNPJd29Dabe1t13ZBrP37c76PwMYt2geaZMTLUSka5w3Rd9_BwPMDFEaNDEcc0zODFFGAZ59ff_zG_83blCU8Wlvt-Wn3R-cDwaZwni34VGWS_wHXlZt7Q</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>book_chapter</recordtype><pqid>EBC3073213_24_185</pqid></control><display><type>book_chapter</type><title>Self-Testing of Linear Segments in User-Programmed FPGAs</title><source>Springer Books</source><creator>Tomaszewicz, Pawel</creator><contributor>Grünbacher, Herbert ; Hartenstein, Reiner W ; Grünbacher, Herbert ; Hartenstein, Reiner W.</contributor><creatorcontrib>Tomaszewicz, Pawel ; Grünbacher, Herbert ; Hartenstein, Reiner W ; Grünbacher, Herbert ; Hartenstein, Reiner W.</creatorcontrib><description>A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single-or multi-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 9783540678991</identifier><identifier>ISBN: 3540678999</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 3540446141</identifier><identifier>EISBN: 9783540446149</identifier><identifier>DOI: 10.1007/3-540-44614-1_19</identifier><identifier>OCLC: 958521259</identifier><identifier>LCCallNum: QA76.9.S88</identifier><language>eng</language><publisher>Germany: Springer Berlin / Heidelberg</publisher><subject>Applied sciences ; Computer systems ; Electronics ; Exact sciences and technology ; Hardware ; Interfaces ; Linear Segment ; Logic Block ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Test Block ; Test Plan ; Test Session</subject><ispartof>Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, 2000, Vol.1896, p.169-174</ispartof><rights>Springer-Verlag Berlin Heidelberg 2000</rights><rights>2000 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><relation>Lecture Notes in Computer Science</relation></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Uhttps://ebookcentral.proquest.com/covers/3073213-l.jpg</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/3-540-44614-1_19$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/3-540-44614-1_19$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>309,310,779,780,784,789,790,793,4050,4051,27925,38255,41442,42511</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=1382992$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><contributor>Grünbacher, Herbert</contributor><contributor>Hartenstein, Reiner W</contributor><contributor>Grünbacher, Herbert</contributor><contributor>Hartenstein, Reiner W.</contributor><creatorcontrib>Tomaszewicz, Pawel</creatorcontrib><title>Self-Testing of Linear Segments in User-Programmed FPGAs</title><title>Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing</title><description>A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single-or multi-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented.</description><subject>Applied sciences</subject><subject>Computer systems</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Interfaces</subject><subject>Linear Segment</subject><subject>Logic Block</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Test Block</subject><subject>Test Plan</subject><subject>Test Session</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>9783540678991</isbn><isbn>3540678999</isbn><isbn>3540446141</isbn><isbn>9783540446149</isbn><fulltext>true</fulltext><rsrctype>book_chapter</rsrctype><creationdate>2000</creationdate><recordtype>book_chapter</recordtype><recordid>eNotUDtPwzAQNk8RSnfGDKwuPp8dx2OFaEGqRKW2s-UkTgi0SbHLwL_HaXvLSfc97u4j5BHYBBhTz0ilYFSIDAQFA_qC3GOcHAdwSRLIACii0FdkrFU-YJnKtYZrkjBknGol8JYkWuaSA5f6joxD-GKxkCNwnZB85bY1XbtwaLsm7et00XbO-nTlmp3rDiFtu3QTnKdL3zfe7nauSmfL-TQ8kJvaboMbn_uIbGav65c3uviYv79MF3QPOdfDdXkGuuaZLjkgk6UqEJWA0rJCyEyKitWWYcYryZlzVZFXCqWSXFd1oQWOyNPJd29Dabe1t13ZBrP37c76PwMYt2geaZMTLUSka5w3Rd9_BwPMDFEaNDEcc0zODFFGAZ59ff_zG_83blCU8Wlvt-Wn3R-cDwaZwni34VGWS_wHXlZt7Q</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Tomaszewicz, Pawel</creator><general>Springer Berlin / Heidelberg</general><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>FFUUA</scope><scope>IQODW</scope></search><sort><creationdate>2000</creationdate><title>Self-Testing of Linear Segments in User-Programmed FPGAs</title><author>Tomaszewicz, Pawel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p1829-3348619f269c21305c7b33741ca0b45654d0fa0362d520eedb8d7357529dfb943</frbrgroupid><rsrctype>book_chapters</rsrctype><prefilter>book_chapters</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Applied sciences</topic><topic>Computer systems</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Interfaces</topic><topic>Linear Segment</topic><topic>Logic Block</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Test Block</topic><topic>Test Plan</topic><topic>Test Session</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tomaszewicz, Pawel</creatorcontrib><collection>ProQuest Ebook Central - Book Chapters - Demo use only</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tomaszewicz, Pawel</au><au>Grünbacher, Herbert</au><au>Hartenstein, Reiner W</au><au>Grünbacher, Herbert</au><au>Hartenstein, Reiner W.</au><format>book</format><genre>bookitem</genre><ristype>CHAP</ristype><atitle>Self-Testing of Linear Segments in User-Programmed FPGAs</atitle><btitle>Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing</btitle><seriestitle>Lecture Notes in Computer Science</seriestitle><date>2000</date><risdate>2000</risdate><volume>1896</volume><spage>169</spage><epage>174</epage><pages>169-174</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>9783540678991</isbn><isbn>3540678999</isbn><eisbn>3540446141</eisbn><eisbn>9783540446149</eisbn><abstract>A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single-or multi-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented.</abstract><cop>Germany</cop><pub>Springer Berlin / Heidelberg</pub><doi>10.1007/3-540-44614-1_19</doi><oclcid>958521259</oclcid><tpages>6</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, 2000, Vol.1896, p.169-174 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_1382992 |
| source | Springer Books |
| subjects | Applied sciences Computer systems Electronics Exact sciences and technology Hardware Interfaces Linear Segment Logic Block Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Test Block Test Plan Test Session |
| title | Self-Testing of Linear Segments in User-Programmed FPGAs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T03%3A04%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_pasca&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=bookitem&rft.atitle=Self-Testing%20of%20Linear%20Segments%20in%20User-Programmed%20FPGAs&rft.btitle=Field-Programmable%20Logic%20and%20Applications:%20The%20Roadmap%20to%20Reconfigurable%20Computing&rft.au=Tomaszewicz,%20Pawel&rft.date=2000&rft.volume=1896&rft.spage=169&rft.epage=174&rft.pages=169-174&rft.issn=0302-9743&rft.eissn=1611-3349&rft.isbn=9783540678991&rft.isbn_list=3540678999&rft_id=info:doi/10.1007/3-540-44614-1_19&rft_dat=%3Cproquest_pasca%3EEBC3073213_24_185%3C/proquest_pasca%3E%3Curl%3E%3C/url%3E&rft.eisbn=3540446141&rft.eisbn_list=9783540446149&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=EBC3073213_24_185&rft_id=info:pmid/&rfr_iscdi=true |