Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we explore an architectural idea to reduce leakage power in data caches. Previous work has shown that cache frames are “dead”...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kaxiras, Stefanos, Hu, Zhigang, Narlikar, Girija, McLellan, Rae
Format:	Buchkapitel
Sprache:	eng
Schlagworte:	Active Ratio Applied sciences Cache Block Cache Line Data Cache Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Leakage Power Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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