An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1989-10, Vol.24 (5), p.1390-1396
Hauptverfasser:	Yamaguchi, K., Nanbu, H., Kanetani, K., Homma, N., Nakamura, T., Ohhata, K., Uchida, A., Ogiue, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	ACTINIDES ALPHA SOURCES AMERICIUM Applied sciences Clamps DATA Decoding DESIGN Driver circuits ELECTRICAL EQUIPMENT Electrodes Electronics ELEMENTS ENGINEERING Exact sciences and technology EXPERIMENTAL DATA INFORMATION Integrated circuits Integrated circuits by function (including memories and processors) ION SOURCES Life estimation MEMORY DEVICES METALS NUMERICAL DATA PARTICLE SOURCES RADIATION SOURCES Random access memory Read-write memory RESISTORS SEMICONDUCTOR DEVICES Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SEMIMETALS SILICON Switching circuits THERMIONIC EMITTERS TRANSISTORS TRANSPLUTONIUM ELEMENTS TRANSURANIUM ELEMENTS 426000 > Engineering-- Components, Electron Devices & Circuits-- (1990-)
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