Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade
We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Int...
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| Veröffentlicht in: | Journal of instrumentation 2020-03, Vol.15 (3), p.T03005-T03005 |
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| container_end_page | T03005 |
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| container_title | Journal of instrumentation |
| container_volume | 15 |
| creator | Chen, C. Gong, D. Guo, D. Huang, G. Huang, X. Kulis, S. Leroux, P. Liu, C. Liu, T. Moreira, P. Prinzie, J. Sun, Q. Wang, P. Xiao, L. Ye, J. |
| description | We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy. |
| doi_str_mv | 10.1088/1748-0221/15/03/T03005 |
| format | Article |
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GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.</description><identifier>ISSN: 1748-0221</identifier><identifier>EISSN: 1748-0221</identifier><identifier>DOI: 10.1088/1748-0221/15/03/T03005</identifier><language>eng</language><publisher>Bristol: IOP Publishing</publisher><subject>Analogue electronic circuits ; Application specific integrated circuits ; Cables ; Channels ; CMOS ; Data recovery ; Electronic detector readout concepts (solid-state) ; Front-end electronics for detector readout ; Integrated circuits ; Modules ; Optical receivers ; OTHER INSTRUMENTATION ; Pixels ; Power consumption ; Transceivers ; Upstream ; Vibration ; VLSI circuits</subject><ispartof>Journal of instrumentation, 2020-03, Vol.15 (3), p.T03005-T03005</ispartof><rights>Copyright IOP Publishing Mar 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c450t-22bbee39ee031f0862e856c3843f4f0774a6d9165a00a96acf38e62e1f5a36333</citedby><cites>FETCH-LOGICAL-c450t-22bbee39ee031f0862e856c3843f4f0774a6d9165a00a96acf38e62e1f5a36333</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,314,778,782,883,27907,27908</link.rule.ids><backlink>$$Uhttps://www.osti.gov/servlets/purl/1685045$$D View this record in Osti.gov$$Hfree_for_read</backlink></links><search><creatorcontrib>Chen, C.</creatorcontrib><creatorcontrib>Gong, D.</creatorcontrib><creatorcontrib>Guo, D.</creatorcontrib><creatorcontrib>Huang, G.</creatorcontrib><creatorcontrib>Huang, X.</creatorcontrib><creatorcontrib>Kulis, S.</creatorcontrib><creatorcontrib>Leroux, P.</creatorcontrib><creatorcontrib>Liu, C.</creatorcontrib><creatorcontrib>Liu, T.</creatorcontrib><creatorcontrib>Moreira, P.</creatorcontrib><creatorcontrib>Prinzie, J.</creatorcontrib><creatorcontrib>Sun, Q.</creatorcontrib><creatorcontrib>Wang, P.</creatorcontrib><creatorcontrib>Xiao, L.</creatorcontrib><creatorcontrib>Ye, J.</creatorcontrib><creatorcontrib>Harvard Univ., Cambridge, MA (United States)</creatorcontrib><title>Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade</title><title>Journal of instrumentation</title><description>We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.</description><subject>Analogue electronic circuits</subject><subject>Application specific integrated circuits</subject><subject>Cables</subject><subject>Channels</subject><subject>CMOS</subject><subject>Data recovery</subject><subject>Electronic detector readout concepts (solid-state)</subject><subject>Front-end electronics for detector readout</subject><subject>Integrated circuits</subject><subject>Modules</subject><subject>Optical receivers</subject><subject>OTHER INSTRUMENTATION</subject><subject>Pixels</subject><subject>Power consumption</subject><subject>Transceivers</subject><subject>Upstream</subject><subject>Vibration</subject><subject>VLSI circuits</subject><issn>1748-0221</issn><issn>1748-0221</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNpNkFtLAzEQhYMoWKt_QYI-rzvZbPbyWIo3KPhgfQ5pdtKm1s2aZEX99aZUxKczzPmYORxCLhncMGianNVlk0FRsJyJHHi-BA4gjsjkzzj-N5-SsxC2CWhFCRPSzTfKKx3R228VreupM1TRtV2rlY00etUHjfYDPTXO07hBOlsuZs_U9n3aJV-_Jh3sJ-5ohxF1TJhH1bkx0nFYe9XhOTkxahfw4len5OXudjl_yBZP94_z2SLTpYCYFcVqhchbRODMQFMV2IhK86bkpjRQ16WqupZVQgGotlLa8AYTxIxQvOKcT8nV4a4L0cqgbYqz0S4l1VGyqhFQigRdH6DBu_cRQ5RbN_o-5ZJFeiXqAniRqOpAae9C8Gjk4O2b8l-SgdzXLveNyn2jkgkJXB5q5z-3pHUf</recordid><startdate>20200301</startdate><enddate>20200301</enddate><creator>Chen, C.</creator><creator>Gong, D.</creator><creator>Guo, D.</creator><creator>Huang, G.</creator><creator>Huang, X.</creator><creator>Kulis, S.</creator><creator>Leroux, P.</creator><creator>Liu, C.</creator><creator>Liu, T.</creator><creator>Moreira, P.</creator><creator>Prinzie, J.</creator><creator>Sun, Q.</creator><creator>Wang, P.</creator><creator>Xiao, L.</creator><creator>Ye, J.</creator><general>IOP Publishing</general><general>Institute of Physics (IOP)</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>OIOZB</scope><scope>OTOTI</scope></search><sort><creationdate>20200301</creationdate><title>Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade</title><author>Chen, C. ; Gong, D. ; Guo, D. ; Huang, G. ; Huang, X. ; Kulis, S. ; Leroux, P. ; Liu, C. ; Liu, T. ; Moreira, P. ; Prinzie, J. ; Sun, Q. ; Wang, P. ; Xiao, L. ; Ye, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c450t-22bbee39ee031f0862e856c3843f4f0774a6d9165a00a96acf38e62e1f5a36333</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Analogue electronic circuits</topic><topic>Application specific integrated circuits</topic><topic>Cables</topic><topic>Channels</topic><topic>CMOS</topic><topic>Data recovery</topic><topic>Electronic detector readout concepts (solid-state)</topic><topic>Front-end electronics for detector readout</topic><topic>Integrated circuits</topic><topic>Modules</topic><topic>Optical receivers</topic><topic>OTHER INSTRUMENTATION</topic><topic>Pixels</topic><topic>Power consumption</topic><topic>Transceivers</topic><topic>Upstream</topic><topic>Vibration</topic><topic>VLSI circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chen, C.</creatorcontrib><creatorcontrib>Gong, D.</creatorcontrib><creatorcontrib>Guo, D.</creatorcontrib><creatorcontrib>Huang, G.</creatorcontrib><creatorcontrib>Huang, X.</creatorcontrib><creatorcontrib>Kulis, S.</creatorcontrib><creatorcontrib>Leroux, P.</creatorcontrib><creatorcontrib>Liu, C.</creatorcontrib><creatorcontrib>Liu, T.</creatorcontrib><creatorcontrib>Moreira, P.</creatorcontrib><creatorcontrib>Prinzie, J.</creatorcontrib><creatorcontrib>Sun, Q.</creatorcontrib><creatorcontrib>Wang, P.</creatorcontrib><creatorcontrib>Xiao, L.</creatorcontrib><creatorcontrib>Ye, J.</creatorcontrib><creatorcontrib>Harvard Univ., Cambridge, MA (United States)</creatorcontrib><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>OSTI.GOV - Hybrid</collection><collection>OSTI.GOV</collection><jtitle>Journal of instrumentation</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chen, C.</au><au>Gong, D.</au><au>Guo, D.</au><au>Huang, G.</au><au>Huang, X.</au><au>Kulis, S.</au><au>Leroux, P.</au><au>Liu, C.</au><au>Liu, T.</au><au>Moreira, P.</au><au>Prinzie, J.</au><au>Sun, Q.</au><au>Wang, P.</au><au>Xiao, L.</au><au>Ye, J.</au><aucorp>Harvard Univ., Cambridge, MA (United States)</aucorp><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade</atitle><jtitle>Journal of instrumentation</jtitle><date>2020-03-01</date><risdate>2020</risdate><volume>15</volume><issue>3</issue><spage>T03005</spage><epage>T03005</epage><pages>T03005-T03005</pages><issn>1748-0221</issn><eissn>1748-0221</eissn><abstract>We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. 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| source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
| subjects | Analogue electronic circuits Application specific integrated circuits Cables Channels CMOS Data recovery Electronic detector readout concepts (solid-state) Front-end electronics for detector readout Integrated circuits Modules Optical receivers OTHER INSTRUMENTATION Pixels Power consumption Transceivers Upstream Vibration VLSI circuits |
| title | Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade |
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