Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiO x /GeO x surface layers, where the GeO x -rich layer is beneath a SiO x -rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiO x and GeO x regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiO x –GeO x interface layer causes large interface trap densities (D it) due to distorted Ge–O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiO x /GeO x , in a selective fashion, leaving an ultrathin SiO x interfacial layer that exhibits dramatically reduced D it.