Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

© 2016, Springer Science+Business Media New York. Aggressive power supply voltage Vddscaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vddresults to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal Vddcondition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.