Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have pro...

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Veröffentlicht in:	Japanese Journal of Applied Physics 2018-04, Vol.57 (4S), p.4
Hauptverfasser:	Kukita, Kentaro, Uechi, Tadayoshi, Shimokawa, Junji, Goto, Masakazu, Yokota, Yoshinori, Kawanaka, Shigeru, Tanamoto, Tetsufumi, Tanimoto, Hiroyoshi, Takagi, Shinichi
Format:	Artikel
Sprache:	eng
Schlagworte:	CAD CMOS Computer aided design Computer simulation Field effect transistors Implantation Low voltage MOSFETs Semiconductor devices Silicon
Online-Zugang:	Volltext
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