Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

We observed an increase of Vth by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of re...

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Veröffentlicht in:	Japanese Journal of Applied Physics 2015-04, Vol.54 (4S), p.4-1-04DD03-4
Hauptverfasser:	Kang, Duckseoung, Lee, Kyunghwan, Kwon, Sangjin, Kim, Shinhyung, Hwang, Yuchul, Shin, Hyungcheol
Format:	Artikel
Sprache:	eng
Schlagworte:	Charge Coefficients Cycles Deterioration Disturbances Flash memory (computers) Gain Mathematical models
Online-Zugang:	Volltext
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