A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access me...

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Veröffentlicht in:	Japanese Journal of Applied Physics 2023-04, Vol.62 (SC), p.SC1085
Hauptverfasser:	Wang, Yun-Yuan, Lin, Yu-Hsuan, Lee, Dai-Ying, Lu, Cheng-Hsien, Wei, Ming-Liang, Tseng, Po-Hao, Lee, Ming-Hsiu, Hsieh, Kuang-Yeu, Wang, Keh-Chung, Lu, Chih-Yuan
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Annealing annealing machine Combinatorial analysis combinatorial optimization Coupling fully-connected Ising model in-memory computing non-volatile memory Optimization Static random access memory Threshold voltage
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