A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm
We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access me...
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| Veröffentlicht in: | Japanese Journal of Applied Physics 2023-04, Vol.62 (SC), p.SC1085 |
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| container_issue | SC |
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| container_title | Japanese Journal of Applied Physics |
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| creator | Wang, Yun-Yuan Lin, Yu-Hsuan Lee, Dai-Ying Lu, Cheng-Hsien Wei, Ming-Liang Tseng, Po-Hao Lee, Ming-Hsiu Hsieh, Kuang-Yeu Wang, Keh-Chung Lu, Chih-Yuan |
| description | We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage (
V
th
) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size. |
| doi_str_mv | 10.35848/1347-4065/acbc2c |
| format | Article |
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V
th
) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.</description><identifier>ISSN: 0021-4922</identifier><identifier>EISSN: 1347-4065</identifier><identifier>DOI: 10.35848/1347-4065/acbc2c</identifier><identifier>CODEN: JJAPB6</identifier><language>eng</language><publisher>Tokyo: IOP Publishing</publisher><subject>Algorithms ; Annealing ; annealing machine ; Combinatorial analysis ; combinatorial optimization ; Coupling ; fully-connected Ising model ; in-memory computing ; non-volatile memory ; Optimization ; Static random access memory ; Threshold voltage</subject><ispartof>Japanese Journal of Applied Physics, 2023-04, Vol.62 (SC), p.SC1085</ispartof><rights>2023 The Japan Society of Applied Physics</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c340t-dec4495ec21eb893b5e181be5c584ebf7092ff8945a86a4438e2460014f847013</cites><orcidid>0000-0001-8352-3584</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.35848/1347-4065/acbc2c/pdf$$EPDF$$P50$$Giop$$H</linktopdf><link.rule.ids>314,776,780,27901,27902,53821,53868</link.rule.ids></links><search><creatorcontrib>Wang, Yun-Yuan</creatorcontrib><creatorcontrib>Lin, Yu-Hsuan</creatorcontrib><creatorcontrib>Lee, Dai-Ying</creatorcontrib><creatorcontrib>Lu, Cheng-Hsien</creatorcontrib><creatorcontrib>Wei, Ming-Liang</creatorcontrib><creatorcontrib>Tseng, Po-Hao</creatorcontrib><creatorcontrib>Lee, Ming-Hsiu</creatorcontrib><creatorcontrib>Hsieh, Kuang-Yeu</creatorcontrib><creatorcontrib>Wang, Keh-Chung</creatorcontrib><creatorcontrib>Lu, Chih-Yuan</creatorcontrib><title>A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm</title><title>Japanese Journal of Applied Physics</title><addtitle>Jpn. J. Appl. Phys</addtitle><description>We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage (
V
th
) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.</description><subject>Algorithms</subject><subject>Annealing</subject><subject>annealing machine</subject><subject>Combinatorial analysis</subject><subject>combinatorial optimization</subject><subject>Coupling</subject><subject>fully-connected Ising model</subject><subject>in-memory computing</subject><subject>non-volatile memory</subject><subject>Optimization</subject><subject>Static random access memory</subject><subject>Threshold voltage</subject><issn>0021-4922</issn><issn>1347-4065</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><recordid>eNp1kEtLAzEUhYMoWB8_wF3AlWBsksnMZJal-IKCC3UdMpmbNiXzMDNj6dZfbmpFNwqBcJLvnJschC4YvUlSKeSUJSIngmbpVJvScHOAJj9Hh2hCKWdEFJwfo5O-X0eZpYJN0McMr9xyRcBaZxw0ZnuNA3inSw-4Hv3gPLyDxysdqo0OQLQx4CHoASqsmwZ0FHjjhhV2DamhbsMW951rsGnHzrtmGakqirrzUEMz6HgfQEezX7Yh-uozdGS17-H8ez9Fr3e3L_MHsni6f5zPFsQkgg6kAiNEkYLhDEpZJGUKTLISUhP_D6XNacGtlYVItcy0EIkELjJKmbBS5JQlp-hyn9uF9m2EflDrdgxNHKl4LjnPipzySLE9ZULb9wGs6oKr46sVo-qrarXrVe16Vfuqo-dq73Ft9xu6XutOZVw9z-NiVKaqq2xkyR_s_9mfFhKRFw</recordid><startdate>20230401</startdate><enddate>20230401</enddate><creator>Wang, Yun-Yuan</creator><creator>Lin, Yu-Hsuan</creator><creator>Lee, Dai-Ying</creator><creator>Lu, Cheng-Hsien</creator><creator>Wei, Ming-Liang</creator><creator>Tseng, Po-Hao</creator><creator>Lee, Ming-Hsiu</creator><creator>Hsieh, Kuang-Yeu</creator><creator>Wang, Keh-Chung</creator><creator>Lu, Chih-Yuan</creator><general>IOP Publishing</general><general>Japanese Journal of Applied Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-8352-3584</orcidid></search><sort><creationdate>20230401</creationdate><title>A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm</title><author>Wang, Yun-Yuan ; Lin, Yu-Hsuan ; Lee, Dai-Ying ; Lu, Cheng-Hsien ; Wei, Ming-Liang ; Tseng, Po-Hao ; Lee, Ming-Hsiu ; Hsieh, Kuang-Yeu ; Wang, Keh-Chung ; Lu, Chih-Yuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c340t-dec4495ec21eb893b5e181be5c584ebf7092ff8945a86a4438e2460014f847013</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Algorithms</topic><topic>Annealing</topic><topic>annealing machine</topic><topic>Combinatorial analysis</topic><topic>combinatorial optimization</topic><topic>Coupling</topic><topic>fully-connected Ising model</topic><topic>in-memory computing</topic><topic>non-volatile memory</topic><topic>Optimization</topic><topic>Static random access memory</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Wang, Yun-Yuan</creatorcontrib><creatorcontrib>Lin, Yu-Hsuan</creatorcontrib><creatorcontrib>Lee, Dai-Ying</creatorcontrib><creatorcontrib>Lu, Cheng-Hsien</creatorcontrib><creatorcontrib>Wei, Ming-Liang</creatorcontrib><creatorcontrib>Tseng, Po-Hao</creatorcontrib><creatorcontrib>Lee, Ming-Hsiu</creatorcontrib><creatorcontrib>Hsieh, Kuang-Yeu</creatorcontrib><creatorcontrib>Wang, Keh-Chung</creatorcontrib><creatorcontrib>Lu, Chih-Yuan</creatorcontrib><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Japanese Journal of Applied Physics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Wang, Yun-Yuan</au><au>Lin, Yu-Hsuan</au><au>Lee, Dai-Ying</au><au>Lu, Cheng-Hsien</au><au>Wei, Ming-Liang</au><au>Tseng, Po-Hao</au><au>Lee, Ming-Hsiu</au><au>Hsieh, Kuang-Yeu</au><au>Wang, Keh-Chung</au><au>Lu, Chih-Yuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm</atitle><jtitle>Japanese Journal of Applied Physics</jtitle><addtitle>Jpn. J. Appl. Phys</addtitle><date>2023-04-01</date><risdate>2023</risdate><volume>62</volume><issue>SC</issue><spage>SC1085</spage><pages>SC1085-</pages><issn>0021-4922</issn><eissn>1347-4065</eissn><coden>JJAPB6</coden><abstract>We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage (
V
th
) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.</abstract><cop>Tokyo</cop><pub>IOP Publishing</pub><doi>10.35848/1347-4065/acbc2c</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0001-8352-3584</orcidid><oa>free_for_read</oa></addata></record> |
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| ispartof | Japanese Journal of Applied Physics, 2023-04, Vol.62 (SC), p.SC1085 |
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| source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
| subjects | Algorithms Annealing annealing machine Combinatorial analysis combinatorial optimization Coupling fully-connected Ising model in-memory computing non-volatile memory Optimization Static random access memory Threshold voltage |
| title | A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm |
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