Experimental demonstration of high-gain CMOS inverter operation at low V dd down to 0.5 V consisting of WSe2 n/p FETs

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Veröffentlicht in:	Japanese Journal of Applied Physics 2022-05, Vol.61 (SC)
Hauptverfasser:	Kawanago, Takamasa, Matsuzaki, Takahiro, Kajikawa, Ryosuke, Muneta, Iriya, Hoshii, Takuya, Kakushima, Kuniyuki, Tsutsui, Kazuo, Wakabayashi, Hitoshi
Format:	Artikel
Sprache:	eng
Schlagworte:	CMOS Inverter TMDC WSe2 FET
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creator	Kawanago, Takamasa Matsuzaki, Takahiro Kajikawa, Ryosuke Muneta, Iriya Hoshii, Takuya Kakushima, Kuniyuki Tsutsui, Kazuo Wakabayashi, Hitoshi
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source	Institute of Physics Journals
subjects	CMOS Inverter TMDC WSe2 FET
title	Experimental demonstration of high-gain CMOS inverter operation at low V dd down to 0.5 V consisting of WSe2 n/p FETs
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