Design Considerations into Circuit Applications for Structurally Optimised FinFET
FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underla...
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Veröffentlicht in: | ECS journal of solid state science and technology 2023-12, Vol.12 (12), p.123007 |
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container_title | ECS journal of solid state science and technology |
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creator | Sarangam, K. Valasa, Sresta Mudidhe, Praveen Kumar Narendar, Vadthiya Kotha, Venkata Ramakrishna Bhukya, Sunitha Bheemudu, V. Pothalaiah, S. |
description | FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (L
g
), fin width (W
fin
) and fin height (H
fin
) for the duak-k spacer FinFET is performed and it is found that lowering the L
g
and W
fin
, and increasing the H
fin
would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155. |
doi_str_mv | 10.1149/2162-8777/ad1619 |
format | Article |
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g
), fin width (W
fin
) and fin height (H
fin
) for the duak-k spacer FinFET is performed and it is found that lowering the L
g
and W
fin
, and increasing the H
fin
would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.</description><identifier>ISSN: 2162-8769</identifier><identifier>EISSN: 2162-8777</identifier><identifier>DOI: 10.1149/2162-8777/ad1619</identifier><identifier>CODEN: EJSSBG</identifier><language>eng</language><publisher>IOP Publishing</publisher><subject>CS amplifier ; dual-k spacer ; FINFET ; inverter ; underlap</subject><ispartof>ECS journal of solid state science and technology, 2023-12, Vol.12 (12), p.123007</ispartof><rights>2023 The Electrochemical Society (“ECS”). Published on behalf of ECS by IOP Publishing Limited</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c313t-ee890a34a40489224ebb4507d1e9496f4a2418de8cecfa5575a4c480c5151ce93</citedby><cites>FETCH-LOGICAL-c313t-ee890a34a40489224ebb4507d1e9496f4a2418de8cecfa5575a4c480c5151ce93</cites><orcidid>0000-0002-2289-6085 ; 0000-0002-0586-9149 ; 0000-0003-4608-760X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.1149/2162-8777/ad1619/pdf$$EPDF$$P50$$Giop$$H</linktopdf><link.rule.ids>314,780,784,27924,27925,53846,53893</link.rule.ids></links><search><creatorcontrib>Sarangam, K.</creatorcontrib><creatorcontrib>Valasa, Sresta</creatorcontrib><creatorcontrib>Mudidhe, Praveen Kumar</creatorcontrib><creatorcontrib>Narendar, Vadthiya</creatorcontrib><creatorcontrib>Kotha, Venkata Ramakrishna</creatorcontrib><creatorcontrib>Bhukya, Sunitha</creatorcontrib><creatorcontrib>Bheemudu, V.</creatorcontrib><creatorcontrib>Pothalaiah, S.</creatorcontrib><title>Design Considerations into Circuit Applications for Structurally Optimised FinFET</title><title>ECS journal of solid state science and technology</title><addtitle>JSS</addtitle><addtitle>ECS J. Solid State Sci. Technol</addtitle><description>FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (L
g
), fin width (W
fin
) and fin height (H
fin
) for the duak-k spacer FinFET is performed and it is found that lowering the L
g
and W
fin
, and increasing the H
fin
would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.</description><subject>CS amplifier</subject><subject>dual-k spacer</subject><subject>FINFET</subject><subject>inverter</subject><subject>underlap</subject><issn>2162-8769</issn><issn>2162-8777</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><recordid>eNp1UMFqwzAMNWODla73HX3cYVktx4ntY8nWbVAoY9vZuI4zHNIk2M6hf7-ElJ42IZCQ3ntID6F7IE8ATK4p5DQRnPO1LiEHeYUWl9H1pc_lLVqFUJMxcsF4Shfo49kG99PiomuDK63X0Y0ddm3scOG8GVzEm75vnDlvqs7jz-gHEwevm-aE9310Rxdsibeu3b583aGbSjfBrs51ib7HafGW7Pav78Vml5gU0phYKyTRKdOMMCEpZfZwYBnhJVjJZF4xTRmI0gpjTaWzjGeaGSaIySADY2W6RGTWNb4LwdtK9d4dtT8pIGpyRU1vq8kCNbsyUh5miut6VXeDb8cDVR2CAjpnSghXfVmN0Mc_oP8q_wKvV3DE</recordid><startdate>20231201</startdate><enddate>20231201</enddate><creator>Sarangam, K.</creator><creator>Valasa, Sresta</creator><creator>Mudidhe, Praveen Kumar</creator><creator>Narendar, Vadthiya</creator><creator>Kotha, Venkata Ramakrishna</creator><creator>Bhukya, Sunitha</creator><creator>Bheemudu, V.</creator><creator>Pothalaiah, S.</creator><general>IOP Publishing</general><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-2289-6085</orcidid><orcidid>https://orcid.org/0000-0002-0586-9149</orcidid><orcidid>https://orcid.org/0000-0003-4608-760X</orcidid></search><sort><creationdate>20231201</creationdate><title>Design Considerations into Circuit Applications for Structurally Optimised FinFET</title><author>Sarangam, K. ; Valasa, Sresta ; Mudidhe, Praveen Kumar ; Narendar, Vadthiya ; Kotha, Venkata Ramakrishna ; Bhukya, Sunitha ; Bheemudu, V. ; Pothalaiah, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c313t-ee890a34a40489224ebb4507d1e9496f4a2418de8cecfa5575a4c480c5151ce93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CS amplifier</topic><topic>dual-k spacer</topic><topic>FINFET</topic><topic>inverter</topic><topic>underlap</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sarangam, K.</creatorcontrib><creatorcontrib>Valasa, Sresta</creatorcontrib><creatorcontrib>Mudidhe, Praveen Kumar</creatorcontrib><creatorcontrib>Narendar, Vadthiya</creatorcontrib><creatorcontrib>Kotha, Venkata Ramakrishna</creatorcontrib><creatorcontrib>Bhukya, Sunitha</creatorcontrib><creatorcontrib>Bheemudu, V.</creatorcontrib><creatorcontrib>Pothalaiah, S.</creatorcontrib><collection>CrossRef</collection><jtitle>ECS journal of solid state science and technology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Sarangam, K.</au><au>Valasa, Sresta</au><au>Mudidhe, Praveen Kumar</au><au>Narendar, Vadthiya</au><au>Kotha, Venkata Ramakrishna</au><au>Bhukya, Sunitha</au><au>Bheemudu, V.</au><au>Pothalaiah, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design Considerations into Circuit Applications for Structurally Optimised FinFET</atitle><jtitle>ECS journal of solid state science and technology</jtitle><stitle>JSS</stitle><addtitle>ECS J. Solid State Sci. Technol</addtitle><date>2023-12-01</date><risdate>2023</risdate><volume>12</volume><issue>12</issue><spage>123007</spage><pages>123007-</pages><issn>2162-8769</issn><eissn>2162-8777</eissn><coden>EJSSBG</coden><abstract>FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (L
g
), fin width (W
fin
) and fin height (H
fin
) for the duak-k spacer FinFET is performed and it is found that lowering the L
g
and W
fin
, and increasing the H
fin
would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.</abstract><pub>IOP Publishing</pub><doi>10.1149/2162-8777/ad1619</doi><tpages>8</tpages><orcidid>https://orcid.org/0000-0002-2289-6085</orcidid><orcidid>https://orcid.org/0000-0002-0586-9149</orcidid><orcidid>https://orcid.org/0000-0003-4608-760X</orcidid></addata></record> |
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source | Institute of Physics Journals |
subjects | CS amplifier dual-k spacer FINFET inverter underlap |
title | Design Considerations into Circuit Applications for Structurally Optimised FinFET |
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