Design Considerations into Circuit Applications for Structurally Optimised FinFET

FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underla...

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Veröffentlicht in:ECS journal of solid state science and technology 2023-12, Vol.12 (12), p.123007
Hauptverfasser: Sarangam, K., Valasa, Sresta, Mudidhe, Praveen Kumar, Narendar, Vadthiya, Kotha, Venkata Ramakrishna, Bhukya, Sunitha, Bheemudu, V., Pothalaiah, S.
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container_issue 12
container_start_page 123007
container_title ECS journal of solid state science and technology
container_volume 12
creator Sarangam, K.
Valasa, Sresta
Mudidhe, Praveen Kumar
Narendar, Vadthiya
Kotha, Venkata Ramakrishna
Bhukya, Sunitha
Bheemudu, V.
Pothalaiah, S.
description FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (L g ), fin width (W fin ) and fin height (H fin ) for the duak-k spacer FinFET is performed and it is found that lowering the L g and W fin , and increasing the H fin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.
doi_str_mv 10.1149/2162-8777/ad1619
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source Institute of Physics Journals
subjects CS amplifier
dual-k spacer
FINFET
inverter
underlap
title Design Considerations into Circuit Applications for Structurally Optimised FinFET
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