A Study of Polysilicon Gate Etch Uniformity in 300 mm Silicon Wafers

Experimental data show that the polysilicon gate length tends to be smaller in the middle of the silicon wafer and also at the silicon wafer edge. This can be seen from electrical measurement data of MOS transistors in a row along a diameter of the wafer. In-line CD (critical dimension) data will also be presented to support the above claim. Physical mechanisms responsible for the experimental observation will be provided. Possible existence of plasma instability during the polysilicon gate etch process will also be discussed.