Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes

The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at...

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Veröffentlicht in:Electronics letters 2020-02, Vol.56 (4), p.199-201
Hauptverfasser: Fan, Lin-Jie, Bi, Jin-Shun, Xu, Yan-Nan, Xi, Kai, Ma, Yao, Liu, Ming, Majumdar, Sandip
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container_end_page 201
container_issue 4
container_start_page 199
container_title Electronics letters
container_volume 56
creator Fan, Lin-Jie
Bi, Jin-Shun
Xu, Yan-Nan
Xi, Kai
Ma, Yao
Liu, Ming
Majumdar, Sandip
description The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole–Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.
doi_str_mv 10.1049/el.2019.3229
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fullrecord <record><control><sourceid>wiley_24P</sourceid><recordid>TN_cdi_iet_journals_10_1049_el_2019_3229</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>ELL2BF06866</sourcerecordid><originalsourceid>FETCH-LOGICAL-c3436-2c6080e1528fd377b6e2a00f0df691b31c558387f7ad8fd75f63c7233be790853</originalsourceid><addsrcrecordid>eNp90D1PwzAQBmALgURVuvEDPDAwkHC2YycZS2gBKaJDQWKzHMcuRvmSE4Ty70kpA0PFdMM9d7p7EbokEBKI0ltThRRIGjJK0xM0I4xDkBLydopmAIQFnKTROVr0vSuARCQSEJEZ2mZ-bHemcRrrd-WVHox3vRpc2-DWYs5xU-Pt5nmz_envTDB41XWu2eHa1K0fsWvwMsOqKfF9huu2NP0FOrOq6s3it87R63r1kj0G-ebhKVvmgWYREwHVAhIwhNPEliyOC2GoArBQWpGSghHNecKS2MaqnETMrWA6powVJk4h4WyObg57tW_73hsrO-9q5UdJQO4zkaaS-0zkPpOJ8wP_cpUZ_7Vylef0bg0iEWKauzrMOTPIj_bTN9NTk_jDu9JO7PoIO3rJN_vdevk</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes</title><source>Wiley-Blackwell Open Access Titles</source><creator>Fan, Lin-Jie ; Bi, Jin-Shun ; Xu, Yan-Nan ; Xi, Kai ; Ma, Yao ; Liu, Ming ; Majumdar, Sandip</creator><creatorcontrib>Fan, Lin-Jie ; Bi, Jin-Shun ; Xu, Yan-Nan ; Xi, Kai ; Ma, Yao ; Liu, Ming ; Majumdar, Sandip</creatorcontrib><description>The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole–Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.</description><identifier>ISSN: 0013-5194</identifier><identifier>ISSN: 1350-911X</identifier><identifier>EISSN: 1350-911X</identifier><identifier>DOI: 10.1049/el.2019.3229</identifier><language>eng</language><publisher>The Institution of Engineering and Technology</publisher><subject>AC mode ; cryogenic characterisation ; cryogenic conditions ; cryogenic electronics ; cryogenic temperatures ; DC modes ; direct voltage ; direct voltage sweeping ; electrical responses ; elemental semiconductors ; integrated circuit reliability ; low‐temperature techniques ; memory window ; on‐state current ; Poole‐Frenkel effect ; Poole–Frenkel effect suppression ; pre‐tunnelling electron quantity ; programming efficiency ; pulse voltage ; random‐access storage ; read curve ; Semiconductor technology ; silicon ; silicon compounds ; silicon–oxide–nitride–oxide–silicon memory cells ; SiON‐Si ; size 55.0 nm ; SONOS ; SONOS charge‐trapping memory ; subthreshold swing ; threshold voltage ; tunnelling</subject><ispartof>Electronics letters, 2020-02, Vol.56 (4), p.199-201</ispartof><rights>The Institution of Engineering and Technology</rights><rights>2020 The Institution of Engineering and Technology</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c3436-2c6080e1528fd377b6e2a00f0df691b31c558387f7ad8fd75f63c7233be790853</citedby><cites>FETCH-LOGICAL-c3436-2c6080e1528fd377b6e2a00f0df691b31c558387f7ad8fd75f63c7233be790853</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1049%2Fel.2019.3229$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1049%2Fel.2019.3229$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,776,780,1411,11542,27903,27904,45553,45554,46030,46454</link.rule.ids><linktorsrc>$$Uhttps://onlinelibrary.wiley.com/doi/abs/10.1049%2Fel.2019.3229$$EView_record_in_Wiley-Blackwell$$FView_record_in_$$GWiley-Blackwell</linktorsrc></links><search><creatorcontrib>Fan, Lin-Jie</creatorcontrib><creatorcontrib>Bi, Jin-Shun</creatorcontrib><creatorcontrib>Xu, Yan-Nan</creatorcontrib><creatorcontrib>Xi, Kai</creatorcontrib><creatorcontrib>Ma, Yao</creatorcontrib><creatorcontrib>Liu, Ming</creatorcontrib><creatorcontrib>Majumdar, Sandip</creatorcontrib><title>Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes</title><title>Electronics letters</title><description>The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole–Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.</description><subject>AC mode</subject><subject>cryogenic characterisation</subject><subject>cryogenic conditions</subject><subject>cryogenic electronics</subject><subject>cryogenic temperatures</subject><subject>DC modes</subject><subject>direct voltage</subject><subject>direct voltage sweeping</subject><subject>electrical responses</subject><subject>elemental semiconductors</subject><subject>integrated circuit reliability</subject><subject>low‐temperature techniques</subject><subject>memory window</subject><subject>on‐state current</subject><subject>Poole‐Frenkel effect</subject><subject>Poole–Frenkel effect suppression</subject><subject>pre‐tunnelling electron quantity</subject><subject>programming efficiency</subject><subject>pulse voltage</subject><subject>random‐access storage</subject><subject>read curve</subject><subject>Semiconductor technology</subject><subject>silicon</subject><subject>silicon compounds</subject><subject>silicon–oxide–nitride–oxide–silicon memory cells</subject><subject>SiON‐Si</subject><subject>size 55.0 nm</subject><subject>SONOS</subject><subject>SONOS charge‐trapping memory</subject><subject>subthreshold swing</subject><subject>threshold voltage</subject><subject>tunnelling</subject><issn>0013-5194</issn><issn>1350-911X</issn><issn>1350-911X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNp90D1PwzAQBmALgURVuvEDPDAwkHC2YycZS2gBKaJDQWKzHMcuRvmSE4Ty70kpA0PFdMM9d7p7EbokEBKI0ltThRRIGjJK0xM0I4xDkBLydopmAIQFnKTROVr0vSuARCQSEJEZ2mZ-bHemcRrrd-WVHox3vRpc2-DWYs5xU-Pt5nmz_envTDB41XWu2eHa1K0fsWvwMsOqKfF9huu2NP0FOrOq6s3it87R63r1kj0G-ebhKVvmgWYREwHVAhIwhNPEliyOC2GoArBQWpGSghHNecKS2MaqnETMrWA6powVJk4h4WyObg57tW_73hsrO-9q5UdJQO4zkaaS-0zkPpOJ8wP_cpUZ_7Vylef0bg0iEWKauzrMOTPIj_bTN9NTk_jDu9JO7PoIO3rJN_vdevk</recordid><startdate>20200220</startdate><enddate>20200220</enddate><creator>Fan, Lin-Jie</creator><creator>Bi, Jin-Shun</creator><creator>Xu, Yan-Nan</creator><creator>Xi, Kai</creator><creator>Ma, Yao</creator><creator>Liu, Ming</creator><creator>Majumdar, Sandip</creator><general>The Institution of Engineering and Technology</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20200220</creationdate><title>Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes</title><author>Fan, Lin-Jie ; Bi, Jin-Shun ; Xu, Yan-Nan ; Xi, Kai ; Ma, Yao ; Liu, Ming ; Majumdar, Sandip</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3436-2c6080e1528fd377b6e2a00f0df691b31c558387f7ad8fd75f63c7233be790853</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>AC mode</topic><topic>cryogenic characterisation</topic><topic>cryogenic conditions</topic><topic>cryogenic electronics</topic><topic>cryogenic temperatures</topic><topic>DC modes</topic><topic>direct voltage</topic><topic>direct voltage sweeping</topic><topic>electrical responses</topic><topic>elemental semiconductors</topic><topic>integrated circuit reliability</topic><topic>low‐temperature techniques</topic><topic>memory window</topic><topic>on‐state current</topic><topic>Poole‐Frenkel effect</topic><topic>Poole–Frenkel effect suppression</topic><topic>pre‐tunnelling electron quantity</topic><topic>programming efficiency</topic><topic>pulse voltage</topic><topic>random‐access storage</topic><topic>read curve</topic><topic>Semiconductor technology</topic><topic>silicon</topic><topic>silicon compounds</topic><topic>silicon–oxide–nitride–oxide–silicon memory cells</topic><topic>SiON‐Si</topic><topic>size 55.0 nm</topic><topic>SONOS</topic><topic>SONOS charge‐trapping memory</topic><topic>subthreshold swing</topic><topic>threshold voltage</topic><topic>tunnelling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Fan, Lin-Jie</creatorcontrib><creatorcontrib>Bi, Jin-Shun</creatorcontrib><creatorcontrib>Xu, Yan-Nan</creatorcontrib><creatorcontrib>Xi, Kai</creatorcontrib><creatorcontrib>Ma, Yao</creatorcontrib><creatorcontrib>Liu, Ming</creatorcontrib><creatorcontrib>Majumdar, Sandip</creatorcontrib><collection>CrossRef</collection><jtitle>Electronics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fan, Lin-Jie</au><au>Bi, Jin-Shun</au><au>Xu, Yan-Nan</au><au>Xi, Kai</au><au>Ma, Yao</au><au>Liu, Ming</au><au>Majumdar, Sandip</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes</atitle><jtitle>Electronics letters</jtitle><date>2020-02-20</date><risdate>2020</risdate><volume>56</volume><issue>4</issue><spage>199</spage><epage>201</epage><pages>199-201</pages><issn>0013-5194</issn><issn>1350-911X</issn><eissn>1350-911X</eissn><abstract>The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole–Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.</abstract><pub>The Institution of Engineering and Technology</pub><doi>10.1049/el.2019.3229</doi><tpages>3</tpages></addata></record>
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source Wiley-Blackwell Open Access Titles
subjects AC mode
cryogenic characterisation
cryogenic conditions
cryogenic electronics
cryogenic temperatures
DC modes
direct voltage
direct voltage sweeping
electrical responses
elemental semiconductors
integrated circuit reliability
low‐temperature techniques
memory window
on‐state current
Poole‐Frenkel effect
Poole–Frenkel effect suppression
pre‐tunnelling electron quantity
programming efficiency
pulse voltage
random‐access storage
read curve
Semiconductor technology
silicon
silicon compounds
silicon–oxide–nitride–oxide–silicon memory cells
SiON‐Si
size 55.0 nm
SONOS
SONOS charge‐trapping memory
subthreshold swing
threshold voltage
tunnelling
title Cryogenic characterisation of 55 nm SONOS charge-trapping memory in AC and DC modes
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T22%3A45%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-wiley_24P&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Cryogenic%20characterisation%20of%2055%20nm%20SONOS%20charge-trapping%20memory%20in%20AC%20and%20DC%20modes&rft.jtitle=Electronics%20letters&rft.au=Fan,%20Lin-Jie&rft.date=2020-02-20&rft.volume=56&rft.issue=4&rft.spage=199&rft.epage=201&rft.pages=199-201&rft.issn=0013-5194&rft.eissn=1350-911X&rft_id=info:doi/10.1049/el.2019.3229&rft_dat=%3Cwiley_24P%3EELL2BF06866%3C/wiley_24P%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true