Hybrid interconnect network for on-chip low-power clock distribution
Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as...
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| Veröffentlicht in: | Electronics letters 2019-03, Vol.55 (5), p.244-246 |
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| creator | Ding, Q Mak, T |
| description | Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers, $\lt $ |
| doi_str_mv | 10.1049/el.2018.6570 |
| format | Article |
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However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers, $\lt $<33 ps of clock skew at 2.5 GHz input with highly unbalanced loads could be found within the proposed CDN, and hence, indicates a promising potential of future high-performance on-chip clock distribution.</description><identifier>ISSN: 0013-5194</identifier><identifier>ISSN: 1350-911X</identifier><identifier>EISSN: 1350-911X</identifier><identifier>DOI: 10.1049/el.2018.6570</identifier><language>eng</language><publisher>The Institution of Engineering and Technology</publisher><subject>CDN ; Circuits and systems ; clock distribution network ; clock distribution networks ; clock skew ; clock uncertainties ; CMOS digital integrated circuits ; CMOS technology ; cornerstone tapered H‐tree model ; delay reduction ; frequency 2.5 GHz ; high‐quality global clock signal ; hybrid interconnect network ; integrated circuit design ; integrated circuit interconnections ; integrated circuit metallisation ; integrated wireless clock transceivers ; low‐power electronics ; metallic interconnect ; modulation technique ; on‐chip low‐power clock distribution ; propagation delay ; synchronous digital integrated circuits ; time 130.0 ps to 400.0 ps ; transceivers</subject><ispartof>Electronics letters, 2019-03, Vol.55 (5), p.244-246</ispartof><rights>The Institution of Engineering and Technology</rights><rights>2020 The Institution of Engineering and Technology</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c3819-3d7489a3133a368b7f82b7a991ab8ec3b1bebf0d644803f610171c2b67ee44bc3</citedby><cites>FETCH-LOGICAL-c3819-3d7489a3133a368b7f82b7a991ab8ec3b1bebf0d644803f610171c2b67ee44bc3</cites><orcidid>0000-0001-7434-8075</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1049%2Fel.2018.6570$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1049%2Fel.2018.6570$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,776,780,1411,11541,27901,27902,45550,45551,46027,46451</link.rule.ids><linktorsrc>$$Uhttps://onlinelibrary.wiley.com/doi/abs/10.1049%2Fel.2018.6570$$EView_record_in_Wiley-Blackwell$$FView_record_in_$$GWiley-Blackwell</linktorsrc></links><search><creatorcontrib>Ding, Q</creatorcontrib><creatorcontrib>Mak, T</creatorcontrib><title>Hybrid interconnect network for on-chip low-power clock distribution</title><title>Electronics letters</title><description>Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers, $\lt $<33 ps of clock skew at 2.5 GHz input with highly unbalanced loads could be found within the proposed CDN, and hence, indicates a promising potential of future high-performance on-chip clock distribution.</description><subject>CDN</subject><subject>Circuits and systems</subject><subject>clock distribution network</subject><subject>clock distribution networks</subject><subject>clock skew</subject><subject>clock uncertainties</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS technology</subject><subject>cornerstone tapered H‐tree model</subject><subject>delay reduction</subject><subject>frequency 2.5 GHz</subject><subject>high‐quality global clock signal</subject><subject>hybrid interconnect network</subject><subject>integrated circuit design</subject><subject>integrated circuit interconnections</subject><subject>integrated circuit metallisation</subject><subject>integrated wireless clock transceivers</subject><subject>low‐power electronics</subject><subject>metallic interconnect</subject><subject>modulation technique</subject><subject>on‐chip low‐power clock distribution</subject><subject>propagation delay</subject><subject>synchronous digital integrated circuits</subject><subject>time 130.0 ps to 400.0 ps</subject><subject>transceivers</subject><issn>0013-5194</issn><issn>1350-911X</issn><issn>1350-911X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><recordid>eNp9kLFOwzAURS0EElXpxgd4YGDAxS92HHuE0lKkSCwgsVmxYwvTEEdOqqh_T6syMADTW869V-8gdAl0DpSrW9fMMwpyLvKCnqAJsJwSBfB2iiaUAiM5KH6OZn0fDAUOXFAOE_Sw3pkUahzawSUb29bZAbduGGPaYB8Tji2x76HDTRxJF0eXsG2i3eA69EMKZjuE2F6gM181vZt93yl6XS1fFmtSPj8-Le5KYpkERVhdcKkqBoxVTEhTeJmZolIKKiOdZQaMM57WgnNJmRdAoQCbGVE4x7mxbIpujr02xb5Pzusuhc8q7TRQfZCgXaMPEvRBwh7Pj_gYGrf7l9XLsszuV1Rkmdrnro-54Ab9Ebep3T_118TVL-iy_NHc1Z59AZmAeFQ</recordid><startdate>20190307</startdate><enddate>20190307</enddate><creator>Ding, Q</creator><creator>Mak, T</creator><general>The Institution of Engineering and Technology</general><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0001-7434-8075</orcidid></search><sort><creationdate>20190307</creationdate><title>Hybrid interconnect network for on-chip low-power clock distribution</title><author>Ding, Q ; Mak, T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3819-3d7489a3133a368b7f82b7a991ab8ec3b1bebf0d644803f610171c2b67ee44bc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CDN</topic><topic>Circuits and systems</topic><topic>clock distribution network</topic><topic>clock distribution networks</topic><topic>clock skew</topic><topic>clock uncertainties</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS technology</topic><topic>cornerstone tapered H‐tree model</topic><topic>delay reduction</topic><topic>frequency 2.5 GHz</topic><topic>high‐quality global clock signal</topic><topic>hybrid interconnect network</topic><topic>integrated circuit design</topic><topic>integrated circuit interconnections</topic><topic>integrated circuit metallisation</topic><topic>integrated wireless clock transceivers</topic><topic>low‐power electronics</topic><topic>metallic interconnect</topic><topic>modulation technique</topic><topic>on‐chip low‐power clock distribution</topic><topic>propagation delay</topic><topic>synchronous digital integrated circuits</topic><topic>time 130.0 ps to 400.0 ps</topic><topic>transceivers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ding, Q</creatorcontrib><creatorcontrib>Mak, T</creatorcontrib><collection>CrossRef</collection><jtitle>Electronics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ding, Q</au><au>Mak, T</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hybrid interconnect network for on-chip low-power clock distribution</atitle><jtitle>Electronics letters</jtitle><date>2019-03-07</date><risdate>2019</risdate><volume>55</volume><issue>5</issue><spage>244</spage><epage>246</epage><pages>244-246</pages><issn>0013-5194</issn><issn>1350-911X</issn><eissn>1350-911X</eissn><abstract>Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers, $\lt $<33 ps of clock skew at 2.5 GHz input with highly unbalanced loads could be found within the proposed CDN, and hence, indicates a promising potential of future high-performance on-chip clock distribution.</abstract><pub>The Institution of Engineering and Technology</pub><doi>10.1049/el.2018.6570</doi><tpages>3</tpages><orcidid>https://orcid.org/0000-0001-7434-8075</orcidid><oa>free_for_read</oa></addata></record> |
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| ispartof | Electronics letters, 2019-03, Vol.55 (5), p.244-246 |
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| language | eng |
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| source | Wiley Online Library Open Access |
| subjects | CDN Circuits and systems clock distribution network clock distribution networks clock skew clock uncertainties CMOS digital integrated circuits CMOS technology cornerstone tapered H‐tree model delay reduction frequency 2.5 GHz high‐quality global clock signal hybrid interconnect network integrated circuit design integrated circuit interconnections integrated circuit metallisation integrated wireless clock transceivers low‐power electronics metallic interconnect modulation technique on‐chip low‐power clock distribution propagation delay synchronous digital integrated circuits time 130.0 ps to 400.0 ps transceivers |
| title | Hybrid interconnect network for on-chip low-power clock distribution |
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