Formal verification of timed VHDL programs

The verification of timed digital circuits is an important issue. These circuits are composed by logical gates, each of them being associated with propagation delays. The analysis of such circuits is necessary to identify critical path and adjust the clock period of the circuit or to determine the s...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bara, A, Bazargan-Sabet, P, Chevallier, R, Encrenaz, E, Ledu, D, Renault, P
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automata theory Computer Science Computer-aided logic design Digital circuit design, modelling and testing Formal methods Logic circuits
Online-Zugang:	Volltext
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