A hardware implementation of a binary neural image processor
The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP...
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| creator | Kennedy, J.V Austin, J Cass, B |
| description | The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220×220 pixels at 25-Hz frame rates. |
| doi_str_mv | 10.1049/cp:19950702 |
| format | Conference Proceeding |
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| fulltext | fulltext |
| identifier | ISBN: 0852966423 |
| ispartof | Fifth International Conference on Image Processing and its Applications, 1995, p.465-469 |
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| language | eng |
| recordid | cdi_iet_conferences_10_1049_cp_19950702 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer vision and image processing techniques Digital signal processing chips Microprocessors and microcomputers Neural computing techniques Neural nets (circuit implementations) Optical information, image and video signal processing Parallel architecture Pattern recognition and computer vision equipment Semiconductor integrated circuits |
| title | A hardware implementation of a binary neural image processor |
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