A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2023-04, Vol.58 (4), p.1074-1086 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Dickson, Timothy O. Deniz, Zeynep Toprak Cochet, Martin Beukema, Troy J. Kossel, Marcel Morf, Thomas Choi, Young-Ho Francese, Pier Andrea Brandli, Matthias Baks, Christian W. Proesel, Jonathan E. Bulzacchelli, John F. Beakes, Michael P. Yoo, Byoung-Joo Ahn, Hyoungbae Lim, Dong-Hyuk Kang, Gunil Park, Sang-Hune Meghelli, Mounir Rhew, Hyo Gyuem Friedman, Daniel J. Choi, Michael Soyuer, Mehmet Shin, Jongshin |
| description | This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply. |
| doi_str_mv | 10.1109/JSSC.2022.3228632 |
| format | Article |
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The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2022.3228632</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bandwidth ; Clocks ; CMOS ; Digital to analog converters ; digital-to-analog converter (DAC) ; Frequency domain analysis ; Modulation ; Nonlinearity ; OFDM ; Orthogonal Frequency Division Multiplexing ; orthogonal frequency-division multiplexing (OFDM) ; pulse amplitude modulation (PAM) ; serializer–deserializer (SerDes) ; source-series terminated (SST) ; Symbols ; Time-domain analysis ; transmitter (TX) ; Transmitters ; Tuning ; wireline</subject><ispartof>IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1074-1086</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. 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| identifier | ISSN: 0018-9200 |
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| issn | 0018-9200 1558-173X |
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| source | IEEE Electronic Library (IEL) |
| subjects | Bandwidth Clocks CMOS Digital to analog converters digital-to-analog converter (DAC) Frequency domain analysis Modulation Nonlinearity OFDM Orthogonal Frequency Division Multiplexing orthogonal frequency-division multiplexing (OFDM) pulse amplitude modulation (PAM) serializer–deserializer (SerDes) source-series terminated (SST) Symbols Time-domain analysis transmitter (TX) Transmitters Tuning wireline |
| title | A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links |
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