Generalized early evaluation in self-timed circuits

Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Thornton, M.A., Fazel, K., Reese, R.B., Traver, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit synthesis Clocks Cost accounting Delay Feedback loop Field programmable gate arrays Logic circuits Logic design Output feedback Throughput
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