A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances

Nonfrequency-dependent transport delay-phase-locked loop (NTD-PLL) is one of the simple grid synchronization approaches that aims to improve the phase and frequency estimation under frequency deviation. However, its amplitude estimation still exhibits double-frequency oscillations that are larger in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on power electronics 2023-04, Vol.38 (4), p.5456-5468
Hauptverfasser: Akhtar, Mohd. Afroz, Saha, Suman, Pal, Dibyendu, Verma, Anant Kumar, Tir, Zoheir
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 5468
container_issue 4
container_start_page 5456
container_title IEEE transactions on power electronics
container_volume 38
creator Akhtar, Mohd. Afroz
Saha, Suman
Pal, Dibyendu
Verma, Anant Kumar
Tir, Zoheir
description Nonfrequency-dependent transport delay-phase-locked loop (NTD-PLL) is one of the simple grid synchronization approaches that aims to improve the phase and frequency estimation under frequency deviation. However, its amplitude estimation still exhibits double-frequency oscillations that are larger in magnitude as compared to the conventional transport delay (TD)-PLL counterpart. To overcome this challenge, two systematic approaches to design amplitude estimators (AEs) for NTD-PLL are presented in this article. One approach includes eliminating double-frequency oscillation error present in \boldsymbol{dq}-frame component {\boldsymbol{\upsilon }}_{\boldsymbol{d}}, whereas another uses Pythagorean trigonometric identity in \boldsymbol{\alpha \beta }-frame for accurate amplitude estimation. Due to the general form of AE proposed in \boldsymbol{\alpha \beta }-frame, it can be easily applied in the design of other TD-based PLLs. The design aspects of these methods are discussed in detail, and the efficacy of the proposed structures is finally evaluated through numerical and experimental results. Some methods to enhance the performance of the AEs are explored and analyzed. This article provides useful insight to the designers regarding the advantages and disadvantages associated with the proposed AEs for their specific applications.
doi_str_mv 10.1109/TPEL.2022.3226242
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_9969135</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9969135</ieee_id><sourcerecordid>2777594876</sourcerecordid><originalsourceid>FETCH-LOGICAL-c245t-b252b6a80a341cd3e66707769f862633281d5ae8769ee7d6ed1188345575e53</originalsourceid><addsrcrecordid>eNo9kNtKw0AQhhdRsFYfQLxZ8Dp1D9mTd6GttRC00Hod0mSiKc3B3a1Qn94NLV4NM_P9c_gRuqdkQikxT5vVPJ0wwtiEMyZZzC7QiJqYRoQSdYlGRGsRaWP4NbpxbkcIjQWhI_Sb4PXReWhyXxc46Xvb5cUX9h2egas_W5w0_b72hxLw3Pk6YJ11uOosftvMolWaPuMV2JA3eVsAXjZhwA800Hr80ZZgcbJth-YeL2xd4lnt_MFuB9bdoqsq3zu4O8cxWr_MN9PXKH1fLKdJGhUsFj7aMsG2Mtck5zEtSg5SKqKUNJWWTHLONC1FDjpUAFQpoaRUax4LoQQIPkaPp6nhsO8DOJ_tuoNtw8KMKaWEiYMyUPREFbZzzkKV9TY8a48ZJdlgcDYYnA0GZ2eDg-bhpKkB4J83RhrKBf8DfD92qg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2777594876</pqid></control><display><type>article</type><title>A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances</title><source>IEEE Electronic Library (IEL)</source><creator>Akhtar, Mohd. Afroz ; Saha, Suman ; Pal, Dibyendu ; Verma, Anant Kumar ; Tir, Zoheir</creator><creatorcontrib>Akhtar, Mohd. Afroz ; Saha, Suman ; Pal, Dibyendu ; Verma, Anant Kumar ; Tir, Zoheir</creatorcontrib><description><![CDATA[Nonfrequency-dependent transport delay-phase-locked loop (NTD-PLL) is one of the simple grid synchronization approaches that aims to improve the phase and frequency estimation under frequency deviation. However, its amplitude estimation still exhibits double-frequency oscillations that are larger in magnitude as compared to the conventional transport delay (TD)-PLL counterpart. To overcome this challenge, two systematic approaches to design amplitude estimators (AEs) for NTD-PLL are presented in this article. One approach includes eliminating double-frequency oscillation error present in <inline-formula><tex-math notation="LaTeX">\boldsymbol{dq}</tex-math></inline-formula>-frame component <inline-formula><tex-math notation="LaTeX">{\boldsymbol{\upsilon }}_{\boldsymbol{d}}</tex-math></inline-formula>, whereas another uses Pythagorean trigonometric identity in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame for accurate amplitude estimation. Due to the general form of AE proposed in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame, it can be easily applied in the design of other TD-based PLLs. The design aspects of these methods are discussed in detail, and the efficacy of the proposed structures is finally evaluated through numerical and experimental results. Some methods to enhance the performance of the AEs are explored and analyzed. This article provides useful insight to the designers regarding the advantages and disadvantages associated with the proposed AEs for their specific applications.]]></description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2022.3226242</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amplitude estimation ; Amplitudes ; Delays ; Design ; Estimation ; Estimators ; Frequency deviation ; Frequency estimation ; Geometry ; Phase locked loops ; phase-locked loop (PLL) ; Pythagorean trigonometric identity (PTI) ; Synchronism ; synchronization ; Time-frequency analysis ; transport-delay</subject><ispartof>IEEE transactions on power electronics, 2023-04, Vol.38 (4), p.5456-5468</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c245t-b252b6a80a341cd3e66707769f862633281d5ae8769ee7d6ed1188345575e53</cites><orcidid>0000-0002-8719-4869 ; 0000-0003-3240-7326 ; 0000-0002-5793-5179</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9969135$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9969135$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Akhtar, Mohd. Afroz</creatorcontrib><creatorcontrib>Saha, Suman</creatorcontrib><creatorcontrib>Pal, Dibyendu</creatorcontrib><creatorcontrib>Verma, Anant Kumar</creatorcontrib><creatorcontrib>Tir, Zoheir</creatorcontrib><title>A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description><![CDATA[Nonfrequency-dependent transport delay-phase-locked loop (NTD-PLL) is one of the simple grid synchronization approaches that aims to improve the phase and frequency estimation under frequency deviation. However, its amplitude estimation still exhibits double-frequency oscillations that are larger in magnitude as compared to the conventional transport delay (TD)-PLL counterpart. To overcome this challenge, two systematic approaches to design amplitude estimators (AEs) for NTD-PLL are presented in this article. One approach includes eliminating double-frequency oscillation error present in <inline-formula><tex-math notation="LaTeX">\boldsymbol{dq}</tex-math></inline-formula>-frame component <inline-formula><tex-math notation="LaTeX">{\boldsymbol{\upsilon }}_{\boldsymbol{d}}</tex-math></inline-formula>, whereas another uses Pythagorean trigonometric identity in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame for accurate amplitude estimation. Due to the general form of AE proposed in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame, it can be easily applied in the design of other TD-based PLLs. The design aspects of these methods are discussed in detail, and the efficacy of the proposed structures is finally evaluated through numerical and experimental results. Some methods to enhance the performance of the AEs are explored and analyzed. This article provides useful insight to the designers regarding the advantages and disadvantages associated with the proposed AEs for their specific applications.]]></description><subject>Amplitude estimation</subject><subject>Amplitudes</subject><subject>Delays</subject><subject>Design</subject><subject>Estimation</subject><subject>Estimators</subject><subject>Frequency deviation</subject><subject>Frequency estimation</subject><subject>Geometry</subject><subject>Phase locked loops</subject><subject>phase-locked loop (PLL)</subject><subject>Pythagorean trigonometric identity (PTI)</subject><subject>Synchronism</subject><subject>synchronization</subject><subject>Time-frequency analysis</subject><subject>transport-delay</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kNtKw0AQhhdRsFYfQLxZ8Dp1D9mTd6GttRC00Hod0mSiKc3B3a1Qn94NLV4NM_P9c_gRuqdkQikxT5vVPJ0wwtiEMyZZzC7QiJqYRoQSdYlGRGsRaWP4NbpxbkcIjQWhI_Sb4PXReWhyXxc46Xvb5cUX9h2egas_W5w0_b72hxLw3Pk6YJ11uOosftvMolWaPuMV2JA3eVsAXjZhwA800Hr80ZZgcbJth-YeL2xd4lnt_MFuB9bdoqsq3zu4O8cxWr_MN9PXKH1fLKdJGhUsFj7aMsG2Mtck5zEtSg5SKqKUNJWWTHLONC1FDjpUAFQpoaRUax4LoQQIPkaPp6nhsO8DOJ_tuoNtw8KMKaWEiYMyUPREFbZzzkKV9TY8a48ZJdlgcDYYnA0GZ2eDg-bhpKkB4J83RhrKBf8DfD92qg</recordid><startdate>20230401</startdate><enddate>20230401</enddate><creator>Akhtar, Mohd. Afroz</creator><creator>Saha, Suman</creator><creator>Pal, Dibyendu</creator><creator>Verma, Anant Kumar</creator><creator>Tir, Zoheir</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8719-4869</orcidid><orcidid>https://orcid.org/0000-0003-3240-7326</orcidid><orcidid>https://orcid.org/0000-0002-5793-5179</orcidid></search><sort><creationdate>20230401</creationdate><title>A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances</title><author>Akhtar, Mohd. Afroz ; Saha, Suman ; Pal, Dibyendu ; Verma, Anant Kumar ; Tir, Zoheir</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c245t-b252b6a80a341cd3e66707769f862633281d5ae8769ee7d6ed1188345575e53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Amplitude estimation</topic><topic>Amplitudes</topic><topic>Delays</topic><topic>Design</topic><topic>Estimation</topic><topic>Estimators</topic><topic>Frequency deviation</topic><topic>Frequency estimation</topic><topic>Geometry</topic><topic>Phase locked loops</topic><topic>phase-locked loop (PLL)</topic><topic>Pythagorean trigonometric identity (PTI)</topic><topic>Synchronism</topic><topic>synchronization</topic><topic>Time-frequency analysis</topic><topic>transport-delay</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Akhtar, Mohd. Afroz</creatorcontrib><creatorcontrib>Saha, Suman</creatorcontrib><creatorcontrib>Pal, Dibyendu</creatorcontrib><creatorcontrib>Verma, Anant Kumar</creatorcontrib><creatorcontrib>Tir, Zoheir</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Mechanical &amp; Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Akhtar, Mohd. Afroz</au><au>Saha, Suman</au><au>Pal, Dibyendu</au><au>Verma, Anant Kumar</au><au>Tir, Zoheir</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2023-04-01</date><risdate>2023</risdate><volume>38</volume><issue>4</issue><spage>5456</spage><epage>5468</epage><pages>5456-5468</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract><![CDATA[Nonfrequency-dependent transport delay-phase-locked loop (NTD-PLL) is one of the simple grid synchronization approaches that aims to improve the phase and frequency estimation under frequency deviation. However, its amplitude estimation still exhibits double-frequency oscillations that are larger in magnitude as compared to the conventional transport delay (TD)-PLL counterpart. To overcome this challenge, two systematic approaches to design amplitude estimators (AEs) for NTD-PLL are presented in this article. One approach includes eliminating double-frequency oscillation error present in <inline-formula><tex-math notation="LaTeX">\boldsymbol{dq}</tex-math></inline-formula>-frame component <inline-formula><tex-math notation="LaTeX">{\boldsymbol{\upsilon }}_{\boldsymbol{d}}</tex-math></inline-formula>, whereas another uses Pythagorean trigonometric identity in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame for accurate amplitude estimation. Due to the general form of AE proposed in <inline-formula><tex-math notation="LaTeX">\boldsymbol{\alpha \beta }</tex-math></inline-formula>-frame, it can be easily applied in the design of other TD-based PLLs. The design aspects of these methods are discussed in detail, and the efficacy of the proposed structures is finally evaluated through numerical and experimental results. Some methods to enhance the performance of the AEs are explored and analyzed. This article provides useful insight to the designers regarding the advantages and disadvantages associated with the proposed AEs for their specific applications.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2022.3226242</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-8719-4869</orcidid><orcidid>https://orcid.org/0000-0003-3240-7326</orcidid><orcidid>https://orcid.org/0000-0002-5793-5179</orcidid></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0885-8993
ispartof IEEE transactions on power electronics, 2023-04, Vol.38 (4), p.5456-5468
issn 0885-8993
1941-0107
language eng
recordid cdi_ieee_primary_9969135
source IEEE Electronic Library (IEL)
subjects Amplitude estimation
Amplitudes
Delays
Design
Estimation
Estimators
Frequency deviation
Frequency estimation
Geometry
Phase locked loops
phase-locked loop (PLL)
Pythagorean trigonometric identity (PTI)
Synchronism
synchronization
Time-frequency analysis
transport-delay
title A Systematic Approach to Design Amplitude Estimators for NTD-PLL: Performance Improvement Under Abnormal Grid Disturbances
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T23%3A11%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Systematic%20Approach%20to%20Design%20Amplitude%20Estimators%20for%20NTD-PLL:%20Performance%20Improvement%20Under%20Abnormal%20Grid%20Disturbances&rft.jtitle=IEEE%20transactions%20on%20power%20electronics&rft.au=Akhtar,%20Mohd.%20Afroz&rft.date=2023-04-01&rft.volume=38&rft.issue=4&rft.spage=5456&rft.epage=5468&rft.pages=5456-5468&rft.issn=0885-8993&rft.eissn=1941-0107&rft.coden=ITPEE8&rft_id=info:doi/10.1109/TPEL.2022.3226242&rft_dat=%3Cproquest_RIE%3E2777594876%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2777594876&rft_id=info:pmid/&rft_ieee_id=9969135&rfr_iscdi=true