A comprehensive fault model for deep submicron digital circuits

Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay info...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Abraham, J.A., Krishnamachary, A., Tupuri, R.S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Benchmark testing Circuit faults Circuit testing Cost function Delay Digital circuits Electrical fault detection Fault detection Logic circuits Logic testing
Online-Zugang:	Volltext bestellen
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