A comprehensive fault model for deep submicron digital circuits
Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay info...
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| creator | Abraham, J.A. Krishnamachary, A. Tupuri, R.S. |
| description | Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay information to deal with both functionality and performance. We show that tests derived using this model can be used to effectively screen chips for defects which affect the functionality and performance of the chips, and that the approach reduces the test costs and defect levels when compared with conventional approaches. Experimental results on large benchmark circuits are used to demonstrate the usefulness of the approach. |
| doi_str_mv | 10.1109/DELTA.2002.994650 |
| format | Conference Proceeding |
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Experimental results on large benchmark circuits are used to demonstrate the usefulness of the approach.</description><subject>Benchmark testing</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Cost function</subject><subject>Delay</subject><subject>Digital circuits</subject><subject>Electrical fault detection</subject><subject>Fault detection</subject><subject>Logic circuits</subject><subject>Logic testing</subject><isbn>0769514537</isbn><isbn>9780769514536</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKxDAUQAMiqON8gK7yA633NrmJWckwjg8ouBnXQ9rcaKSdlrQV_HuF8WzO7sAR4gahRAR397ir95uyAqhK57QhOBNXYI0j1KTshVhP0xf8oUlbpEvxsJHt0I-ZP_k4pW-W0S_dLPshcCfjkGVgHuW0NH1q83CUIX2k2XeyTbld0jxdi_Pou4nX_16J96fdfvtS1G_Pr9tNXSS0ei5aRAK0MRAzNBSRsTLBaw_3ll2sjGp8pKBYGwukgAx5Vh4wuqpxjVYrcXvqJmY-jDn1Pv8cTovqF27bRzw</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Abraham, J.A.</creator><creator>Krishnamachary, A.</creator><creator>Tupuri, R.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>A comprehensive fault model for deep submicron digital circuits</title><author>Abraham, J.A. ; Krishnamachary, A. ; Tupuri, R.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i174t-c115017fd5ee0b5f1e126da4a087e9f263baf5d3e4670530565ae3a01f92b9b43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Benchmark testing</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Cost function</topic><topic>Delay</topic><topic>Digital circuits</topic><topic>Electrical fault detection</topic><topic>Fault detection</topic><topic>Logic circuits</topic><topic>Logic testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Abraham, J.A.</creatorcontrib><creatorcontrib>Krishnamachary, A.</creatorcontrib><creatorcontrib>Tupuri, R.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Abraham, J.A.</au><au>Krishnamachary, A.</au><au>Tupuri, R.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A comprehensive fault model for deep submicron digital circuits</atitle><btitle>Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002</btitle><stitle>DELTA</stitle><date>2002</date><risdate>2002</risdate><spage>360</spage><epage>364</epage><pages>360-364</pages><isbn>0769514537</isbn><isbn>9780769514536</isbn><abstract>Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay information to deal with both functionality and performance. We show that tests derived using this model can be used to effectively screen chips for defects which affect the functionality and performance of the chips, and that the approach reduces the test costs and defect levels when compared with conventional approaches. Experimental results on large benchmark circuits are used to demonstrate the usefulness of the approach.</abstract><pub>IEEE</pub><doi>10.1109/DELTA.2002.994650</doi><tpages>5</tpages></addata></record> |
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| ispartof | Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, 2002, p.360-364 |
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| language | eng |
| recordid | cdi_ieee_primary_994650 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Benchmark testing Circuit faults Circuit testing Cost function Delay Digital circuits Electrical fault detection Fault detection Logic circuits Logic testing |
| title | A comprehensive fault model for deep submicron digital circuits |
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