Implementation of artificial neural networks on a reconfigurable hardware accelerator
The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing f...
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| creator | Porrmann, M. Witkowski, U. Kalte, H. Ruckert, U. |
| description | The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed. |
| doi_str_mv | 10.1109/EMPDP.2002.994279 |
| format | Conference Proceeding |
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The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed.</description><identifier>ISBN: 9780769514444</identifier><identifier>ISBN: 0769514448</identifier><identifier>DOI: 10.1109/EMPDP.2002.994279</identifier><language>eng</language><publisher>IEEE</publisher><subject>Acceleration ; Artificial neural networks ; Broadcasting ; Field programmable gate arrays ; Memory management ; Neural network hardware ; Postal services ; Prototypes ; Random access memory ; World Wide Web</subject><ispartof>Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, 2002, p.243-250</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/994279$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/994279$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Porrmann, M.</creatorcontrib><creatorcontrib>Witkowski, U.</creatorcontrib><creatorcontrib>Kalte, H.</creatorcontrib><creatorcontrib>Ruckert, U.</creatorcontrib><title>Implementation of artificial neural networks on a reconfigurable hardware accelerator</title><title>Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing</title><addtitle>EMPDP</addtitle><description>The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed.</description><subject>Acceleration</subject><subject>Artificial neural networks</subject><subject>Broadcasting</subject><subject>Field programmable gate arrays</subject><subject>Memory management</subject><subject>Neural network hardware</subject><subject>Postal services</subject><subject>Prototypes</subject><subject>Random access memory</subject><subject>World Wide Web</subject><isbn>9780769514444</isbn><isbn>0769514448</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKAzEYhQMiKHUeQFd5gRlznSRLqVULFbuw6_JP8o9G51IykeLbO7R-m29xDgcOIbecVZwzd7963T5uK8GYqJxTwrgLUjhjmamd5mrmihTT9MVmlFZO2GuyW_eHDnscMuQ4DnRsKaQc2-gjdHTAn3RSPo7pe6JzAWhCPw5t_JijpkP6CSkcISEF77HDBHlMN-SyhW7C4t8LsntavS9fys3b83r5sCkjZyqXrg669dI2GmttvQhoWbCBKSODlYHVJoB1Ajjn2jYoVAAjuGq1USEoWcsFuTvvRkTcH1LsIf3uz9_lH1abUKY</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Porrmann, M.</creator><creator>Witkowski, U.</creator><creator>Kalte, H.</creator><creator>Ruckert, U.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>Implementation of artificial neural networks on a reconfigurable hardware accelerator</title><author>Porrmann, M. ; Witkowski, U. ; Kalte, H. ; Ruckert, U.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-96d5fc38b5e658c2de80d8d0473d83d067da892a11158be24da7214f574dd4363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Acceleration</topic><topic>Artificial neural networks</topic><topic>Broadcasting</topic><topic>Field programmable gate arrays</topic><topic>Memory management</topic><topic>Neural network hardware</topic><topic>Postal services</topic><topic>Prototypes</topic><topic>Random access memory</topic><topic>World Wide Web</topic><toplevel>online_resources</toplevel><creatorcontrib>Porrmann, M.</creatorcontrib><creatorcontrib>Witkowski, U.</creatorcontrib><creatorcontrib>Kalte, H.</creatorcontrib><creatorcontrib>Ruckert, U.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Porrmann, M.</au><au>Witkowski, U.</au><au>Kalte, H.</au><au>Ruckert, U.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementation of artificial neural networks on a reconfigurable hardware accelerator</atitle><btitle>Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing</btitle><stitle>EMPDP</stitle><date>2002</date><risdate>2002</risdate><spage>243</spage><epage>250</epage><pages>243-250</pages><isbn>9780769514444</isbn><isbn>0769514448</isbn><abstract>The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed.</abstract><pub>IEEE</pub><doi>10.1109/EMPDP.2002.994279</doi><tpages>8</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Acceleration Artificial neural networks Broadcasting Field programmable gate arrays Memory management Neural network hardware Postal services Prototypes Random access memory World Wide Web |
| title | Implementation of artificial neural networks on a reconfigurable hardware accelerator |
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