A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are...

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Bibliographische Detailangaben
Hauptverfasser:	Geissler, S., Appenzeller, D., Cohen, E., Charlebois, S., Kartschoke, P., McCormick, P., Rohrer, N., Salem, G., Sandon, P., Singer, B., Von Reyn, T., Zimmerman, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS technology Copper Delay Diodes Frequency Logic Microprocessors Phase locked loops Reduced instruction set computing
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Beschreibung
Zusammenfassung:	Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.
DOI:	10.1109/ISSCC.2002.992979