Fault simulation for VHDL based test bench and BIST evaluation

A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelin...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Farshbaf, H., Zolfy, M., Mirkhani, S., Navabi, Z.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic testing Built-in self-test Circuit faults Circuit simulation Circuit synthesis Circuit testing Computational modeling Fault detection Hardware System testing
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