A 38.64 Gbps Large-CPM 2KB LDPC Decoder Implementation for NAND Flash Memories
The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) cod...
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| Veröffentlicht in: | IEEE open journal of circuits and systems 2022, p.1-1 |
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| creator | Liu, Li-Wei Yuan, Mu-Hua Liao, Yang-Chin Chang, Hsie-Chia |
| description | The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2. |
| doi_str_mv | 10.1109/OJCAS.2022.3203849 |
| format | Article |
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This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. 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This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.</description><subject>Codes</subject><subject>Decoder</subject><subject>Decoding</subject><subject>Error correction codes</subject><subject>Flash memories</subject><subject>Floors</subject><subject>LDPC</subject><subject>NAND</subject><subject>Parity check codes</subject><subject>SSD</subject><subject>Throughput</subject><issn>2644-1225</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><recordid>eNp9ybsOgjAUANDGxESj_IAu9wfA9lIURgTxjSS6m6oXxfBKy-Lfuzg7neEwNhHcEYIHs9MuCs8OckTHRe76MuixIc6ltAWiN2CWMW_OOXpCCFwMWRqC6ztzCetba-Cg9JPsKDsC7pdwiLMIYro3D9KwrdqSKqo71RVNDXmjIQ3TGJJSmRccqWp0QWbM-rkqDVk_R2yarC7Rxi6I6NrqolL6cw38hfSldP_vFzi2OgY</recordid><startdate>2022</startdate><enddate>2022</enddate><creator>Liu, Li-Wei</creator><creator>Yuan, Mu-Hua</creator><creator>Liao, Yang-Chin</creator><creator>Chang, Hsie-Chia</creator><general>IEEE</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><orcidid>https://orcid.org/0000-0002-3575-3657</orcidid><orcidid>https://orcid.org/0000-0001-7954-4219</orcidid><orcidid>https://orcid.org/0000-0002-0525-8129</orcidid></search><sort><creationdate>2022</creationdate><title>A 38.64 Gbps Large-CPM 2KB LDPC Decoder Implementation for NAND Flash Memories</title><author>Liu, Li-Wei ; Yuan, Mu-Hua ; Liao, Yang-Chin ; Chang, Hsie-Chia</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_98748443</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Codes</topic><topic>Decoder</topic><topic>Decoding</topic><topic>Error correction codes</topic><topic>Flash memories</topic><topic>Floors</topic><topic>LDPC</topic><topic>NAND</topic><topic>Parity check codes</topic><topic>SSD</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Li-Wei</creatorcontrib><creatorcontrib>Yuan, Mu-Hua</creatorcontrib><creatorcontrib>Liao, Yang-Chin</creatorcontrib><creatorcontrib>Chang, Hsie-Chia</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><jtitle>IEEE open journal of circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Liu, Li-Wei</au><au>Yuan, Mu-Hua</au><au>Liao, Yang-Chin</au><au>Chang, Hsie-Chia</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 38.64 Gbps Large-CPM 2KB LDPC Decoder Implementation for NAND Flash Memories</atitle><jtitle>IEEE open journal of circuits and systems</jtitle><stitle>OJCAS</stitle><date>2022</date><risdate>2022</risdate><spage>1</spage><epage>1</epage><pages>1-1</pages><eissn>2644-1225</eissn><coden>IOJCC3</coden><abstract>The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. 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| source | IEEE Open Access Journals; DOAJ Directory of Open Access Journals; Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| subjects | Codes Decoder Decoding Error correction codes Flash memories Floors LDPC NAND Parity check codes SSD Throughput |
| title | A 38.64 Gbps Large-CPM 2KB LDPC Decoder Implementation for NAND Flash Memories |
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